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More AXI write/read ordering

Randy Pascarella
Note: This was originally posted on 25th October 2007 at http://forums.arm.com

In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address.  Sounds like the master's assumption upon receipt of BRESP is that a read with an address overlap can be issued and will be ordered beyond AXI behind the write, such that the read returns new data.

However, if there is no address overlap, is the master's assumption that the read may eventually pass the write beyond AXI?

Also, what qualifies as an address overlap?  Is the range of overlap considered to be a hit to the range governed by the AADDR, ASIZE, ALEN, ABURST signals of both the write and read, or something different?

Finally, why is there a distinction between memory regions and peripheral regions in section 8.6 of the spec?  If the master cannot discern between the two, should the most pessimistic view be assumed, which would be assuming a peripheral region?

Thanks!!!
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    Note: This was originally posted on 26th October 2007 at http://forums.arm.com

    Once again, thanks for your helpful responses.  I am being more and more convinced that bufferable writes are akin to PCI Posted Writes in semantics (targeting memory regions, whether a memory controller or device memory with no side-effects) while non-bufferable writes are akin to PCI I/O or Config Writes in semantics (targeting peripheral regions like config space with side-effects), even though the ordering rules are somewhat different.

    I had always thought that an AXI master would burst data to a memory region with the same AWID and issue a non-bufferable write on the last of the burst just to know that a dependent read could be issued (either a producer/consumer flag type of read or a read with address overlap) and to ensure that the writes made it to their destination.

    Now I am assuming that this burst would typically be all bufferable, and the read would end up flushing out the bufferable writes just like PCI.  I am also assuming that non-bufferable write usage would follow along the lines of PCI with, as you mentioned, "control" type semantics.

    Let me know if I'm still off base here.

    Thanks again, very helpful.

    Randy
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    Note: This was originally posted on 26th October 2007 at http://forums.arm.com

    I tried to cover both cases in my earlier reply.

    There doesn't need to be any address overlap, as soon as the master sees a BRESP for any write access, it can assume that transfer has been completed.

    In the simpler address overlap case, any slave that has buffered the write data will have to do hazard checking for subsequent read accesses.

    In a non-overlap case, where I described the write as being a "control" access, as soon as the master sees a BRESP it might attempt a read, assuming the control access has switched whatever needed changing.

    That is why I suggested that this type of "control" write accesses shouldn't be defined as bufferable, so you only get a BRESP when the "control" operation has been performed.

    As for what qualifies as an "address overlap", I would expect this to be the whole address region defined by the AxADDR, AxSIZE, AxLEN and AxBURST controls.

    Finally, the distinction between memory and peripheral regions in the spec is roughly what we have been discussing, namely that memory regions can rely on the AXI slave doing hazard checking against buffered write, but peripheral regions would be I/O type accesses where access ordering may be important with no address overlap detection occurring.

    If you want to have some of the memory map as supporting bufferable accesses, you will need to programme this into the AXI master so that it knows what sort of access types it can use. This will normally be done in some sort of MMU or MPU inside the AXI master.

    So the master AXI interface then does know the difference between peripheral and memory regions, and if it doesn't, it would have to assume all available memory space is non-bufferable to ensure correct ordering if it has RAW or WAW ordering requirements.

    That's my thoughts anyway, maybe someone else will have a different view.

    JD
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    Note: This was originally posted on 29th October 2007 at http://forums.arm.com

    > Let me know if I'm still off base here.

    Hi Randy,

    I can't comment on exact comparisons with PCI as I've never used that bus, but I think we are now in agreement how the bufferable and non-bufferable transactions are used.

    JD