For AXI we are using AWSIZE(unaligned address = AWADDR % 2**AWSIZE). So for APB which size should we use to calculate unaligned address.
The APB protocol doesn't support unaligned transfers, so PADDR must be aligned to width of the data bus. On a 32-bit data bus implementation for example you would see PADDR step up 4 bytes at a time; 0x0, 0x4, 0x8...
When bridging to the APB protocol from other AMBA system buses (perhaps AHB or AXI) you will usually see the LSBs of PADDR are tied low, so meaningless unaligned accesses cannot then be signalled.
If you are using APB4 there is then the PSTRB signal to indicate which of the byte lanes of the data bus contain valid write data, but for read accesses (and write accesses for APB3 and earlier) the full width of the data bus is used for each APB transfer.
Hello sir, I came across a feature of APB4 that it supports unaligned address access so started implementing it. What is the difference between unaligned transfers and unaligned address access. Also is there anything mentioned in APB4 spec about it not supporting unaligned address access?
Where did you see this feature of APB4 described (can you give me an exact document reference) so that I can answer once I understand the context of the description ?
As previously stated, my understanding is that the APB protocol does not support unaligned accesses.
http://www.smart-dv.com/simxl/apb.html
Please refer this link which states unaligned address access as one of the feature for APB4
You might need to contact that company for an explanation of what they mean.
It certainly isn't a "feature" of APB4 that I am aware of.
Surely sir, I will get back to you if anything comes up...thank you for your time!
I want know if it is possible to use pstrb = "0101", "1010" or "1001"
Yes, you can.
You might use these PSTRB values if you only wanted to update 2 of the 4 bytes in a register. This would save having to perform a read/modify/write sequence needed to preserve the bytes you are not updating.