This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor or in the master interface?).
Also, during any point of time, there will be two transfers in two different states (address phase of current transfer coincides with data phase of previous transfer). So will there also be two different state machines deployed at any moment?
I think the answer to this question would be very application specific, not something you could really have a generic reply for.
However...
You could design a state machine to either go through a simple IDLE-ADDRESS-DATA-IDLE sequence to control single accesses to the bus, but that would only be for a very simple master design.
Or you could design a more complex state machine incorporating HTRANS sequences and different HBURST types being used, all working in the address phases of the transfers. I wouldn't normally expect a separate data phase state machine as the data phase of one transfer follows immediatly after the address phase of the same transfers, so simply delaying the address phase state by an HREADY qualified HCLK rising edge would give you the data phase "state".
Sorry, that's about as generic a reply as I can think of, hopefully it addresses some of your questions.
Thanks for the reply, that definitely helped. Still I do have one more question that i probably was not able to convey properly in my post. Suppose we take your example of a simple IDLE-ADDRESS-DATA-IDLE sequence state machine. When the state reaches DATA state, there's already another transfer (next one) in its ADDRESS state. So does this mean two separate state machines are required in order to handle these two transfers? (Because at any point of time, there may be two transfers at most, taking place in two different states.)
My IDLE-ADDRESS-DATA-IDLE example was really thinking of a VERY simple master design which only ever had one ongoing access. The AHB is pipelined, so the data phase of an access coincides with the address phase of the next access, but my simple master thinking was that the master would just be signalling IDLE transfers around NONSEQ accesses, so not having to consider SEQ accesses.
If you are looking at a master which could have 2 active (non-IDLE) transfers ongoing (one in the address phase, one in the data phase), you do really need to be building a state machine just tracking the address phase transfer sequences (mainly using HTRANS), and then register the address phase "state" using an HREADY=1 qualified HCLK rising edge to give you a data phase control (no need for a separate state machine).