I am working on design of APB master and slave connected back to back. Slave component has simple reg with 16 locations
As per APB, for READ/WRITE transaction from master I am generating PSEL = 1 in the first clock cycle and then PENABLE = 1 in the next clock cycle.
During the two clock cycles, PADDR, PWDATA, PWRITE signals does not change. Here APB slave drives PREADY always HIGH. So the PENABLE goes to '0' in the second clock cycle as per the protocol.
Question here is when should APB slave SAMPLE the Control/Data Signals from Master for both READ/WRITE transfers ? Is it in the SETUP phase or the ACCESS phase.
We need to drive the PREADY and PSLVERR and the PRDATA from slave at the same clock for the read transfer (which should happen in the ACCESS phase here).
Hope my query is clear here. Please share inputs.
Hi Colin,
Thanks for the clarification.
APB basic access time is 2 cycles. (1st - SETUP, 2nd - ACCESS PHASE)
For write transfers, we can achieve the 2 cycles completion phase by driving PREADY =1 by default or making it HIGH in the second clock cycle (PSEL = 1 , PWRITE =1 , PENABLE =1) where PADDR , PWDATA is sampled in the second clock cycle. Here we are sure that the data is written to the address specified in the internal register/memory of the slave.
For read transfer, as per earlier details , PADDR is sampled in ACCESS PHASE. So we cant have the PRDATA in the same clock cycle. It takes additional cycle to return the data. So we drive PREADY =1 only when valid data is available. (3rd clock)
As per protocol, to achieve valid PRDATA and PREADY =1 from slave in second clock cylce, PADDR should be sampled in the SETUP phase (first clock cycle) only, but in earlier discussion ,it is indicated to sample paddr during access phase only. So we cant realize if data sampled in access phase. But can be achieved only when sampled in Setup phase (PSEL =1 and PENABLE = 0). As these are NBA assignments it definitely required one cycle to return data.
But I understand that Sampling should be done only during access phase.
In some designs we see that PREADY is driven HIGH all the time. In such scenarios, how do the designer ensure PRDATA is valid in second clock cycle?
I think in my first reply I said "Control signals should be sampled by the peripheral at the end of the setup phase", so this would then allow the peripheral to start driving PRDATA at the start of the access phase, and so allow the transfer to complete at the end of a single cycle access phase if the peripheral's access time allows PRDATA to be valid at the end of that cycle.
This is how read accesses can be completed in 2 cycles, and is how accesses HAD TO work in the first releases of APB where there was no PREADY signal.