I am working on design of APB master and slave connected back to back. Slave component has simple reg with 16 locations
As per APB, for READ/WRITE transaction from master I am generating PSEL = 1 in the first clock cycle and then PENABLE = 1 in the next clock cycle.
During the two clock cycles, PADDR, PWDATA, PWRITE signals does not change. Here APB slave drives PREADY always HIGH. So the PENABLE goes to '0' in the second clock cycle as per the protocol.
Question here is when should APB slave SAMPLE the Control/Data Signals from Master for both READ/WRITE transfers ? Is it in the SETUP phase or the ACCESS phase.
We need to drive the PREADY and PSLVERR and the PRDATA from slave at the same clock for the read transfer (which should happen in the ACCESS phase here).
Hope my query is clear here. Please share inputs.
Control signals should be sampled by the peripheral at the end of the setup phase.
For write transfers the peripheral can then sample PWDATA either at the end of the setup phase (when PSEL=1 and PENABLE=0) or else at the end of the access phase (when PSEL=1 and PENABLE=1). PWDATA is guaranteed to be stable throughout the APB access, so it doesn't really matter when you sample it, although I suppose sampling at the end of the access phase is the intention of the protocol as it allows the peripheral one cycle to detect the transfer and then another cycle to then prepare to sample the data.
For read transfers the PRDATA bus is only valid during the access phase, so when PSEL=1 and PENABLE=1 (and PREADY=1), so the master will only sample read data just before PENABLE goes low at the end of the access.
Hi Colin,
Thanks for the clarification on sampling data on read/write transfers.
First clock : PSEL = 1 & PWRITE = 0/1 (read/write, here PREADY is LOW by default)
Second clock : PSEL =1 & PENABLE = 1 & PWRITE = 0/1 (for write mem[paddr] <= pwdata and for read prdata <= mem[paddr])
Third clock cycle : PREADY =1
For write transfers, the addr/data is sampled when PSEL =1 and PENABLE = 1 (SECOND CLOCK). Later PREADY = 1 is driven in the next clock cycle (which is third clock cycle) where the data is written to the internal registers to make sure both data and PREADY happens at same time.
But this takes three cycles to complete one APB write/read transfer. The same is done with read transfer where PRDATA and PREADY =1 is driven in third clock cycle
If I make PREADY =1 by default, the APB master will complete transfer in TWO clock cycles as per protocol. But PRDATA will be only available in third clock cycle by which time PSEL & PENABLE goes to LOW. So now prdata is not valid for Master.
Please suggest how can we realize making PRDATA have valid data in second clock cycle when PREADY =1 always HIGH.
For your initial descriptions of the first clock and second clock, why can't PREADY be high during the second clock ?
If your memory just needs an enable signal to know when PWDATA should be sampled, this just needs to be when PSEL & PWRITE & PENABLE is 1'b1 if the data input is a latch, or the falling edge of the PSEL & PWRITE & PENABLE logic (both probably also including some PADDR decoding).
If you are using the above logic during the second clock just to know when to sample data, but this isn't written to the actual memory until one cycle later, then you could drive PREADY one cycle later as you describe, but that is something your design requires, not something the protocol requires.
For reads you could start the memory access as soon as PENABLE goes high, so if the memory being accessed can generate valid PRDATA during that single cycle "second clock", again PREADY could also be driven high in this cycle. If PRDATA cannot be driven valid during the second clock cycle, again that is a design issue requiring an extra cycle, not something mandated by the APB spec.
It sounds like your PRDATA not being valid until the third clock cycle is an access time limitation of the register/memory being accessed, so having PREADY allows you to stall the APB access until the peripheral can drive back valid read data, but as you know the address being read at the end of the first clock cycle, the protocol does then allow the peripheral to immediately then start returning read data to be sampled by the APB master at the end of the second cycle, so not requiring 3 cycles.
2 cycles is the basic access timing for APB, PREADY allows you to extend this access timing, but only if the peripheral being accessed needs additional access time.
Thanks for the clarification.
APB basic access time is 2 cycles. (1st - SETUP, 2nd - ACCESS PHASE)
For write transfers, we can achieve the 2 cycles completion phase by driving PREADY =1 by default or making it HIGH in the second clock cycle (PSEL = 1 , PWRITE =1 , PENABLE =1) where PADDR , PWDATA is sampled in the second clock cycle. Here we are sure that the data is written to the address specified in the internal register/memory of the slave.
For read transfer, as per earlier details , PADDR is sampled in ACCESS PHASE. So we cant have the PRDATA in the same clock cycle. It takes additional cycle to return the data. So we drive PREADY =1 only when valid data is available. (3rd clock)
As per protocol, to achieve valid PRDATA and PREADY =1 from slave in second clock cylce, PADDR should be sampled in the SETUP phase (first clock cycle) only, but in earlier discussion ,it is indicated to sample paddr during access phase only. So we cant realize if data sampled in access phase. But can be achieved only when sampled in Setup phase (PSEL =1 and PENABLE = 0). As these are NBA assignments it definitely required one cycle to return data.
But I understand that Sampling should be done only during access phase.
In some designs we see that PREADY is driven HIGH all the time. In such scenarios, how do the designer ensure PRDATA is valid in second clock cycle?
I think in my first reply I said "Control signals should be sampled by the peripheral at the end of the setup phase", so this would then allow the peripheral to start driving PRDATA at the start of the access phase, and so allow the transfer to complete at the end of a single cycle access phase if the peripheral's access time allows PRDATA to be valid at the end of that cycle.
This is how read accesses can be completed in 2 cycles, and is how accesses HAD TO work in the first releases of APB where there was no PREADY signal.