When should APB slave Sample address/Data for read/write transaction from APB master?

For your initial descriptions of the first clock and second clock, why can't PREADY be high during the second clock ?

If your memory just needs an enable signal to know when PWDATA should be sampled, this just needs to be when PSEL & PWRITE & PENABLE is 1'b1 if the data input is a latch, or the falling edge of the PSEL & PWRITE & PENABLE logic (both probably also including some PADDR decoding).

If you are using the above logic during the second clock just to know when to sample data, but this isn't written to the actual memory until one cycle later, then you could drive PREADY one cycle later as you describe, but that is something your design requires, not something the protocol requires.

For reads you could start the memory access as soon as PENABLE goes high, so if the memory being accessed can generate valid PRDATA during that single cycle "second clock", again PREADY could also be driven high in this cycle. If PRDATA cannot be driven valid during the second clock cycle, again that is a design issue requiring an extra cycle, not something mandated by the APB spec.

It sounds like your PRDATA not being valid until the third clock cycle is an access time limitation of the register/memory being accessed, so having PREADY allows you to stall the APB access until the peripheral can drive back valid read data, but as you know the address being read at the end of the first clock cycle, the protocol does then allow the peripheral to immediately then start returning read data to be sampled by the APB master at the end of the second cycle, so not requiring 3 cycles.

2 cycles is the basic access timing for APB, PREADY allows you to extend this access timing, but only if the peripheral being accessed needs additional access time.

For your initial descriptions of the first clock and second clock, why can't PREADY be high during the second clock ?

If your memory just needs an enable signal to know when PWDATA should be sampled, this just needs to be when PSEL & PWRITE & PENABLE is 1'b1 if the data input is a latch, or the falling edge of the PSEL & PWRITE & PENABLE logic (both probably also including some PADDR decoding).

If you are using the above logic during the second clock just to know when to sample data, but this isn't written to the actual memory until one cycle later, then you could drive PREADY one cycle later as you describe, but that is something your design requires, not something the protocol requires.

For reads you could start the memory access as soon as PENABLE goes high, so if the memory being accessed can generate valid PRDATA during that single cycle "second clock", again PREADY could also be driven high in this cycle. If PRDATA cannot be driven valid during the second clock cycle, again that is a design issue requiring an extra cycle, not something mandated by the APB spec.

It sounds like your PRDATA not being valid until the third clock cycle is an access time limitation of the register/memory being accessed, so having PREADY allows you to stall the APB access until the peripheral can drive back valid read data, but as you know the address being read at the end of the first clock cycle, the protocol does then allow the peripheral to immediately then start returning read data to be sampled by the APB master at the end of the second cycle, so not requiring 3 cycles.

2 cycles is the basic access timing for APB, PREADY allows you to extend this access timing, but only if the peripheral being accessed needs additional access time.

Hi Colin,

Thanks for the clarification.

APB basic access time is 2 cycles. (1st - SETUP, 2nd - ACCESS PHASE)

For write transfers, we can achieve the 2 cycles completion phase by driving PREADY =1 by default or making it HIGH in the second clock cycle (PSEL = 1 , PWRITE =1 , PENABLE =1)  where PADDR , PWDATA is sampled in the second clock cycle. Here we are sure that the data is written to the address specified in the internal register/memory of the slave.

For read transfer, as per earlier details , PADDR is sampled in ACCESS PHASE. So we cant have the PRDATA in the same clock cycle. It takes additional cycle to return the data. So we drive PREADY =1 only when valid data is available. (3rd clock)

    As per protocol, to achieve valid PRDATA and PREADY =1 from slave in second clock cylce, PADDR should be sampled in the SETUP phase (first clock cycle) only, but in earlier discussion ,it is indicated to sample paddr during access phase only. So we cant realize if data sampled in access phase. But can be achieved only when sampled in Setup phase (PSEL =1 and PENABLE = 0). As these are NBA assignments it definitely required one cycle to return data. 

But I understand that Sampling should be done only during access phase.

In some designs we see that PREADY is driven HIGH all the time. In such scenarios, how do the designer ensure PRDATA is valid in second clock cycle?

I think in my first reply I said "Control signals should be sampled by the peripheral at the end of the setup phase", so this would then allow the peripheral to start driving PRDATA at the start of the access phase, and so allow the transfer to complete at the end of a single cycle access phase if the peripheral's access time allows PRDATA to be valid at the end of that cycle.

This is how read accesses can be completed in 2 cycles, and is how accesses HAD TO work in the first releases of APB where there was no PREADY signal.