Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction

Hello All,

  I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.

When  I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?

Scenario : Single master single slave only.

Example: I write 32 bit data from 9000_0000 on INCR4. Data is stored at 9000_0000,9000_0004, 9000_0008,9000_000C. INCR4 address as calculated by slave.

D1 to D4 are all 32 bit data.

9000_0000 ---- D1

9000_0004 ----- D2

9000_0008 ----- D3

9000_000C ------ D4

When I read at 9000_0000 with INCR4, I am getting output as 

1st clk  ----  D2 D1

2nd clk ---- D2 D1

3rd clk  ---- D4 D3

4th ck  -----  D4 D3

Question: When I read at 9000_0000, my slave also calculates address in terms of 32 bit only, so why should I not expect the following:

1st clk --- D2 D1

2nd clk --- D3 D2

3rd clk  ---- D4 D3

4th clk ----- RA D4

RA -- stores for random data that is present in the next address. 

Question: When data is being read from memory, why is my data being read twice and not continuous?