Write strobe for AXI4 lite

The AXI4 spec states that AWSIZE is not needed because "All accesses are defined to be the width of the data bus", with only 32-bit and 64-bit data bus widths supported.

Masters can then use WSTRB to signal write data transfers narrower than the width of the implemented data bus, such as the half-word (16-bit) transfers you mention.

All of the WSTRB values you show are legal for a 32-bit data bus implementation, but these wouldn't be considered as normal "half-word" transfers, as those would imply writes to adjacent byte lanes, and to 16-bit aligned byte lanes, so WSTRB values of 0011 or 1100.

Instead what your WSTRB encodings implement are what would be termed as "sparse" writes (writes to non-contiguous byte lanes). They are still legitimate WSTRB encodings, each signalling 2 valid byte lanes, but not normal "half-word" transfers.

So yes, they are valid WSTRB encodings, yes they each transfer 2 bytes, but not a half-word.

The AXI4 spec states that AWSIZE is not needed because "All accesses are defined to be the width of the data bus", with only 32-bit and 64-bit data bus widths supported.

Masters can then use WSTRB to signal write data transfers narrower than the width of the implemented data bus, such as the half-word (16-bit) transfers you mention.

All of the WSTRB values you show are legal for a 32-bit data bus implementation, but these wouldn't be considered as normal "half-word" transfers, as those would imply writes to adjacent byte lanes, and to 16-bit aligned byte lanes, so WSTRB values of 0011 or 1100.

Instead what your WSTRB encodings implement are what would be termed as "sparse" writes (writes to non-contiguous byte lanes). They are still legitimate WSTRB encodings, each signalling 2 valid byte lanes, but not normal "half-word" transfers.

So yes, they are valid WSTRB encodings, yes they each transfer 2 bytes, but not a half-word.