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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 750 Questions
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  • Answered

    In CHI how the Slave side is giving the L-Credits to the Master Side 0

    • AMBA 5 CHI
    • CHI
    • AMBA CHI C2C
    • Network on Chip (NoC)
    2374 views
    3 replies
    Latest 9 months ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Questions about AsyncBridge CDC Verification Using STA (set_max_delay & Clock Latency) 0

    • CPU Architecture
    • Timing
    • System on Chip (SoC)
    • Clocking Structures & Timing Mechanisms
    • Physical Design
    1333 views
    0 replies
    Started 9 months ago
    by Hwang Jaemin
  • Suggested Answer

    Request for Support: Handling Outstanding Transactions and Channel Slice Management 0

    1226 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    CHI G - Txn ID re-use before comp ack being sent in case of ExpCompAck transfers +1

    875 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Compatibility of PWAKEUP of APB completer with Q-channel compliant clock controller 0

    • APB
    • APB Peripherals
    815 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Does BaseR_Cortex-R82 FVP support GICv3 ? 0

    1812 views
    4 replies
    Latest 11 months ago
    by Johnny Lin Arm Employee Badge
  • Suggested Answer

    Segmentation fault on running SystemC executable 0

    • Fixed Virtual Platforms (FVPs)
    • systemc
    1497 views
    3 replies
    Latest over 1 year ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    AHB master starts transactions to a 2nd slave but the 2nd slave is not ready. How will the 2nd slave handle this when it is ready? 0

    • AMBA 3 AHB Interface
    • AMBA 2 AHB Interface
    • AHB
    802 views
    1 reply
    Latest over 1 year ago
    by Manikanth Mithinti
  • Not Answered

    dma-330 validation simulation build error 0

    • dma-330
    531 views
    0 replies
    Started over 1 year ago
    by hanguang yu
  • Answered

    Can MakeInvalid be issued by discarding the issuer's own dirty data? 0

    • AMBA 5 CHI
    • CHI
    1638 views
    1 reply
    Latest over 1 year ago
    by Ben Hicks Arm Employee Badge
  • Answered

    Clarification Required on AHB hrdata Error Response Timing During Read Transaction 0

    • AHB
    1649 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Can a WriteUnique be sent after CompDBIDResp but before CopybackWrData? 0

    • AMBA 5 CHI
    • CHI
    1793 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Correspondence of 1-bit ACTIVE Signal to Different Power Modes in Arm®︎ Power Policy Unit Architecture Specification 0

    • PPU
    • q-channel
    2494 views
    3 replies
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    I'm curious about how INTID calculation works. 0

    • GIC400
    • INTID
    1749 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Debug Message Output Issue in RTL Simulation 0

    • printf
    • debug
    666 views
    0 replies
    Started over 1 year ago
    by ele
  • Answered

    Write Hit in Shared State is there any way where i could do the write operation without wait in for invalidation ACK in ACE 0

    • AMBA
    • ACE
    • ACE-Lite
    • ACE 5
    3148 views
    6 replies
    Latest over 1 year ago
    by Kidilam Firoz
  • Not Answered

    Difficulty Integrating PARSEC Benchmarks with gem5 ARM - Seeking Best Practices 0

    906 views
    0 replies
    Started over 1 year ago
    by RAJASEKAR LAKSHMANAN
  • Answered

    ACE:why writeunqiue/writelineunqiue cant overlap with writeback? 0

    • AMBA
    • ACE
    • Interface
    1387 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    hello,problems that need to be confirmed on the AHBS interface of the Cortex-M7 processor. 0

    • Cortex-M7
    • Cortex-M
    • AHB
    599 views
    0 replies
    Started over 1 year ago
    by ren tianpeng
  • Not Answered

    hello,I have confirmed the problem of using the sie-200 IP ahb synchronous bridge. 0

    • AHB2AHB
    772 views
    0 replies
    Started over 1 year ago
    by ren tianpeng
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