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NIC-400 QVN: W data output gap differs (0/2/1 cycles) across token_prerequest settings

Breez
Hi all,

I'm seeing different write data throughput behavior on NIC-400 (r1p2) with QVN-400, and would like to ask if anyone can help explain.

## Setup

- **NIC-400 r1p2** with QVN-400
- Path: CPU (ASIB) → Switch → DDR (AMIB)
- CPU sends write transactions(len=0) **back-to-back** (0-cycle gap between transactions)
- Three configurations tested:

| Config | QVN        | token_prerequest | DDR W output gap             |
|----------|--------------|-------------------------|-------------------------------------|
| 1         | Disabled | false                      | **0 cycles** (back-to-back) |
| 2         | Enabled  | false                      | **2 cycles**                         |
| 3         | Enabled  | true                       | **1 cycle**                           |

## Key question

Why does `token_prerequest=false` produce a 2-cycle gap, `token_prerequest=true` produces 1-cycle, and no-QVN produces 0-cycle?

## My understanding

- **No QVN**: Data flows one-directionally with no feedback path — pipeline latency doesn't affect throughput, gap = 0.

- **QVN + prereq=false**: Each W beat needs a full token request→grant→return round-trip, gap = 2.

- **QVN + prereq=true**: Token is pre-allocated, eliminating the request round-trip, but W channel doesn't support pre-allocated tokens (only AR/AW do), leaving 1 cycle, gap = 1.

## Questions

1. Is there any other source of W-channel gap in QVN mode besides the token round-trip? (e.g., internal arbitration, VN switching)

2. The W-channel pre-allocated token limitation (AR/AW only, not W) — is this documented in the TRM? I found it in the ARM Community QVN introduction but not in DSU0027H.

3. Any recommendations on how to reduce the W data gap to 0 while keeping QVN enabled?

Any insights appreciated. Thanks!
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