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Hi all. As you know, there is cache in Mail400 and A35 seperately. Do I need to implement hardware cache coherence between them, for example, using CCI.
Hi Ben, I am designing an SOC chip with A35 and mali400. I do not know the data those need to be exchanged between mali400 and A35. If they are just some configurations, then perhaps they can be set as non-cacheable. If they are big data, then maybe it's better to set them as cachable. If the data are set as cachable, then maybe I have to consider the coherence between the cache in mali400 and A35.
Mali-400 doesn't support the CCI hardware coherency protocols, this is only supported in the Bifrost architecture onwards. Any required cache coherency is managed manually in software by the device driver, but this mostly means using uncached memory for data shared with the GPU.
HTH, Pete
Hi Peter, thanks a lot!
Hi Peter, could I raise another question? For Mali G31 and Cortex-A35, can I still use software to maintain the coherency between them?
I see a figure presented by ARM, which display a system with A55,D51,V52,G31 and NIC450. From this figure, it seems there is no need to implement hardware coherency between mali and cpu.Will the management by software affect the performance?