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Is there any cache coherence between Mail400 and CPU

asic_xuan

Hi all. As you know, there is cache in Mail400 and A35 seperately. Do I need to implement hardware cache coherence between them, for example, using CCI.

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  • 0 in reply to Peter Harris

    Hi Peter, could I raise another question? For Mali G31 and Cortex-A35, can I still use software to maintain the coherency between them?

    I see a figure presented by ARM, which display a system with A55,D51,V52,G31 and NIC450. From this figure, it seems there is no need to implement hardware coherency between mali and cpu.Will the management by software affect the performance?

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  • 0 in reply to Peter Harris

    Hi Peter, could I raise another question? For Mali G31 and Cortex-A35, can I still use software to maintain the coherency between them?

    I see a figure presented by ARM, which display a system with A55,D51,V52,G31 and NIC450. From this figure, it seems there is no need to implement hardware coherency between mali and cpu.Will the management by software affect the performance?

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