Hello All,
1. I am interfacing SDRAM MT48LC4M32B2 with LPC2478. I am able to initialize it and test it in main() function without including it in scatter file.
Below is my problem statement........................................................ ..................................................................................... 2. i want use it as DATA, HEAP and STACK sections. hence added in scatter file and initialised in LPC2400.s but it can't work.
Below is scatter file................................................................ ..................................................................................... ; ************************************************************* ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* LR_IROM1 0x00000000 0x00080000 { ; load region size_region ER_IROM1 0x00000000 0x00080000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) }
RW_IRAM1 0x40000000 0x00010000 { .ANY (+RW +ZI) } RW_IRAM2 0x7FE00000 0x00004000 { .ANY (+RW +ZI) }
RW_RAM1 0xA0000000 0x01000000 { ; RW data .ANY (+RW +ZI) }
ARM_LIB_HEAP 0xA0100000 EMPTY 0x8000 { }
ARM_LIB_STACK 0xA0110000 EMPTY -0x8000 { } } scatter file end..................................................................... .....................................................................................
;// Dynamic Memory Interface Setup --------------------------------------- ;// <e> Dynamic Memory Interface Setup EMC_DYNAMIC_SETUP EQU 1 EMC_STATIC_SETUP EQU 0
;// <h> Dynamic Memory Refresh Timer Register (EMCDynamicRefresh) ;// Configures dynamic memory refresh operation ;// <o0.0..10> REFRESH: Refresh timer <0x000-0x7FF> ;// 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS ;// </h> EMC_DYN_RFSH_Val EQU 0x000007FF;01C
;// <h> Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) ;// Configures the dynamic memory read strategy ;// <o0.0..1> RD: Read data strategy ;// <0=> Clock out delayed strategy ;// <1=> Command delayed strategy ;// <2=> Command delayed strategy plus one clock cycle ;// <3=> Command delayed strategy plus two clock cycles ;// </h> EMC_DYN_RD_CFG_Val EQU 0x00000001
EMC_DYN_RP_Val EQU 0x00000002 EMC_DYN_RAS_Val EQU 0x00000003 EMC_DYN_SREX_Val EQU 0x00000007 EMC_DYN_APR_Val EQU 0x00000002 EMC_DYN_DAL_Val EQU 0x00000005 EMC_DYN_WR_Val EQU 0x00000001 EMC_DYN_RC_Val EQU 0x00000005 EMC_DYN_RFC_Val EQU 0x00000005 EMC_DYN_XSR_Val EQU 0x00000007 EMC_DYN_RRD_Val EQU 0x00000001 EMC_DYN_MRD_Val EQU 0x00000002
;// <e> Configure External Bus Behaviour for Dynamic CS0 Area EMC_DYNCS0_SETUP EQU 1 EMC_DYNCS1_SETUP EQU 0 EMC_DYNCS2_SETUP EQU 0 EMC_DYNCS3_SETUP EQU 0
EMC_DYN_CFG0_Val EQU 0x00084400 ;0x00004680
;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0) ;// Controls the RAS and CAS latencies for the dynamic memory CS0 ;// <o0.8..9> CAS: CAS latency ;// <1=> One CCLK cycle ;// <2=> Two CCLK cycles ;// <3=> Three CCLK cycles ;// <o0.0..1> RAS: RAS latency (active to read/write delay) ;// <1=> One CCLK cycle ;// <2=> Two CCLK cycles ;// <3=> Three CCLK cycles ;// </h> EMC_DYN_RASCAS0_Val EQU 0x00000202 ;santosh 0x00000303
;// </e> End of Dynamic Setup for CS0 Area
;// </e> End of Dynamic Setup
;// </e> End of EMC Setup
PRESERVE8
; Area Definition and Entry Point ; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY ARM
;IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ;IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit|
; Exception Vectors ; Mapped to Address 0. ; Absolute addressing mode must be used. ; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors ;LDR PC, Image$$ARM_LIB_STACK$$ZI$$Limit LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector ; LDR PC, IRQ_Addr LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address 0xB8A06F60
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
IMPORT SWI_Handler
Undef_Handler B Undef_Handler ;SWI_Handler B SWI_Handler PAbt_Handler B PAbt_Handler DAbt_Handler B DAbt_Handler IRQ_Handler B IRQ_Handler FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler Reset_Handler
; Clock Setup ------------------------------------------------------------------
; IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) LDR R0, =SCB_BASE MOV R1, #0xAA MOV R2, #0x55
; Configure and Enable PLL LDR R3, =SCS_Val ; Enable main oscillator STR R3, [R0, #SCS_OFS]
IF (SCS_Val:AND:OSCEN) != 0 OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize ANDS R3, R3, #OSCSTAT BEQ OSC_Loop ENDIF
LDR R3, =CLKSRCSEL_Val ; Select PLL source clock STR R3, [R0, #CLKSRCSEL_OFS] LDR R3, =PLLCFG_Val STR R3, [R0, #PLLCFG_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS] MOV R3, #PLLCON_PLLE STR R3, [R0, #PLLCON_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS]
IF (CLKSRCSEL_Val:AND:3) != 2 ; Wait until PLL Locked (if source is not RTC oscillator) PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] ANDS R3, R3, #PLLSTAT_PLOCK BEQ PLL_Loop ELSE ; Wait at least 200 cycles (if source is RTC oscillator) MOV R3, #(200/4) PLL_Loop SUBS R3, R3, #1 BNE PLL_Loop ENDIF
M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) AND R3, R3, R4 LDR R4, =PLLCFG_Val EORS R3, R3, R4 BNE M_N_Lock
; Setup CPU clock divider MOV R3, #CCLKCFG_Val STR R3, [R0, #CCLKCFG_OFS]
; Setup USB clock divider LDR R3, =USBCLKCFG_Val STR R3, [R0, #USBCLKCFG_OFS]
; Setup Peripheral Clock LDR R3, =PCLKSEL0_Val STR R3, [R0, #PCLKSEL0_OFS] LDR R3, =PCLKSEL1_Val STR R3, [R0, #PCLKSEL1_OFS]
; Switch to PLL Clock MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) STR R3, [R0, #PLLCON_OFS] STR R1, [R0, #PLLFEED_OFS] STR R2, [R0, #PLLFEED_OFS] ; ENDIF ; CLOCK_SETUP
; Setup Memory Accelerator Module ----------------------------------------------
IF MAM_SETUP != 0 LDR R0, =MAM_BASE MOV R1, #MAMTIM_Val STR R1, [R0, #MAMTIM_OFS] MOV R1, #MAMCR_Val STR R1, [R0, #MAMCR_OFS] ENDIF ; MAM_SETUP
; Setup External Memory Controller ---------------------------------------------
; IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0) LDR R0, =EMC_BASE LDR R1, =SCB_BASE LDR R2, =PCB_BASE
LDR R4, =EMC_PCONP_Const ; Enable EMC LDR R3, [R1, #PCONP_OFS] ORR R4, R4, R3 STR R4, [R1, #PCONP_OFS]
LDR R4, =EMC_CTRL_Val STR R4, [R0, #EMC_CTRL_OFS] LDR R4, =EMC_CONFIG_Val STR R4, [R0, #EMC_CONFIG_OFS]
; Setup pin functions for External Bus functionality LDR R4, =EMC_PINSEL5_Val STR R4, [R2, #PINSEL5_OFS] LDR R4, =EMC_PINSEL6_Val STR R4, [R2, #PINSEL6_OFS] LDR R4, =EMC_PINSEL7_Val STR R4, [R2, #PINSEL7_OFS] LDR R4, =EMC_PINSEL8_Val STR R4, [R2, #PINSEL8_OFS] LDR R4, =EMC_PINSEL9_Val STR R4, [R2, #PINSEL9_OFS]
; Setup Dynamic Memory Interface ; IF (EMC_DYNAMIC_SETUP != 0)
LDR R4, =EMC_DYN_RP_Val STR R4, [R0, #EMC_DYN_RP_OFS] LDR R4, =EMC_DYN_RAS_Val STR R4, [R0, #EMC_DYN_RAS_OFS] LDR R4, =EMC_DYN_SREX_Val STR R4, [R0, #EMC_DYN_SREX_OFS] LDR R4, =EMC_DYN_APR_Val STR R4, [R0, #EMC_DYN_APR_OFS] LDR R4, =EMC_DYN_DAL_Val STR R4, [R0, #EMC_DYN_DAL_OFS] LDR R4, =EMC_DYN_WR_Val STR R4, [R0, #EMC_DYN_WR_OFS] LDR R4, =EMC_DYN_RC_Val STR R4, [R0, #EMC_DYN_RC_OFS] LDR R4, =EMC_DYN_RFC_Val STR R4, [R0, #EMC_DYN_RFC_OFS] LDR R4, =EMC_DYN_XSR_Val STR R4, [R0, #EMC_DYN_XSR_OFS] LDR R4, =EMC_DYN_RRD_Val STR R4, [R0, #EMC_DYN_RRD_OFS] LDR R4, =EMC_DYN_MRD_Val STR R4, [R0, #EMC_DYN_MRD_OFS]
LDR R4, =EMC_DYN_RD_CFG_Val STR R4, [R0, #EMC_DYN_RD_CFG_OFS]
IF (EMC_DYNCS0_SETUP != 0) LDR R4, =EMC_DYN_RASCAS0_Val STR R4, [R0, #EMC_DYN_RASCAS0_OFS] LDR R4, =EMC_DYN_CFG0_Val MVN R5, #BUFEN_Const AND R4, R4, R5 STR R4, [R0, #EMC_DYN_CFG0_OFS] ENDIF
LDR R6, =1440000 ; Number of cycles to delay Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc
LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command STR R4, [R0, #EMC_DYN_CTRL_OFS]
LDR R6, =2880000 ; Number of cycles to delay Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz BNE Wait_1
LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command STR R4, [R0, #EMC_DYN_CTRL_OFS]
MOV R4, #2 STR R4, [R0, #EMC_DYN_RFSH_OFS]
MOV R6, #64 ; Number of cycles to delay Wait_2 SUBS R6, R6, #1 ; Delay BNE Wait_2
LDR R4, =EMC_DYN_RFSH_Val STR R4, [R0, #EMC_DYN_RFSH_OFS]
LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command STR R4, [R0, #EMC_DYN_CTRL_OFS]
; Dummy read (set SDRAM Mode register) IF (EMC_DYNCS0_SETUP != 0) LDR R4, =DYN_MEM0_BASE ;LDR R5, =(EMC_DYN_RASCAS0_Val:AND:0x00000300) ; get CAS Latency ;LSR R5, #4 ; set CAS Latency (Bit4..6) LDR R5, =(0x22) ;IF ((EMC_DYN_CFG0_Val:AND:0x00004000) != 0) ;ORR R5, R5, #0x02 ; set burst length 4 (Bit0..2) LSL R5, #12 ;ELSE ;ORR R5, R5, #0x03 ; set burst length 8 (Bit0..2) ;LSL R5, #12 ;ENDIF ADD R4, R4, R5 LDR R4, [R4, #0] ENDIF
LDR R4, =NORMAL_CMD ; Write NORMAL Command STR R4, [R0, #EMC_DYN_CTRL_OFS]
; Enable buffer if requested by settings ;IF (EMC_DYNCS0_SETUP != 0):LAND:((0x00080000:AND:BUFEN_Const) != 0);EMC_DYN_CFG0_Val LDR R4, =(0x00084500);EMC_DYN_CFG0_Val STR R4, [R0, #EMC_DYN_CFG0_OFS] ;ENDIF
LDR R6, =1440000;14400 ; Number of cycles to delay Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz BNE Wait_3
; ENDIF ; EMC_DYNAMIC_SETUP
; Setup Static Memory Interface ; ENDIF ; EMC_SETUP
; Copy Exception Vectors to Internal RAM ---------------------------------------
IF :DEF:RAM_INTVEC ADR R8, Vectors ; Source LDR R9, =RAM_BASE ; Destination LDMIA R8!, {R0-R7} ; Load Vectors STMIA R9!, {R0-R7} ; Store Vectors LDMIA R8!, {R0-R7} ; Load Handler Addresses STMIA R9!, {R0-R7} ; Store Handler Addresses ENDIF
; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control IF :DEF:REMAP LDR R0, =MEMMAP IF :DEF:EXTMEM_MODE MOV R1, #3 ELIF :DEF:RAM_MODE MOV R1, #2 ELSE MOV R1, #1 ENDIF STR R1, [R0] ENDIF
; Setup Stack for each mode ----------------------------------------------------
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR IF :DEF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0 SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code -------------------------------------------------------------
IMPORT __main LDR R0, =__main BX R0
IF :DEF:__MICROLIB
EXPORT __heap_base EXPORT __heap_limit
ELSE ; User Initial Stack & Heap ALIGN 4 AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + USR_Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDIF
END
I HAVE ADDED SCATTER FILE AND START UP FILE IN MULTIPLE PART, I WAS NOT ABLE TO ADD ONCE ALL.
Pity you didn't read the posting instructions for source code, or consider using something like pastebin
Before you try to get Keil to place data in the SDRAM you'd be much better validating your initialization code, and TESTING the memory integrity first. If this is a board you have designed you will need to pay attention to the circuit and pins used, and the clock rates, and the geometry and speed of the SDRAM.
Turn off "Run to main()" and step/analyze your startup code with a debugger.