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Using SDRAM MT48LC4M32B2-6 with LPC2478

Hello All,

1. I am interfacing SDRAM MT48LC4M32B2 with LPC2478. I am able to initialize it and test it in main() function without including it in scatter file.

Below is my problem statement........................................................
.....................................................................................
2. i want use it as DATA, HEAP and STACK sections. hence added in scatter file and initialised in LPC2400.s
but it can't work.

Below is scatter file................................................................
.....................................................................................
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00080000 { ; load region size_region ER_IROM1 0x00000000 0x00080000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO)
}

RW_IRAM1 0x40000000 0x00010000
{ .ANY (+RW +ZI)
} RW_IRAM2 0x7FE00000 0x00004000 { .ANY (+RW +ZI)
}

RW_RAM1 0xA0000000 0x01000000 { ; RW data .ANY (+RW +ZI)
}

ARM_LIB_HEAP 0xA0100000 EMPTY 0x8000
{ }

ARM_LIB_STACK 0xA0110000 EMPTY -0x8000
{ }
} scatter file end.....................................................................
.....................................................................................

Parents
  • ; Copy Exception Vectors to Internal RAM ---------------------------------------

    IF :DEF:RAM_INTVEC ADR R8, Vectors ; Source LDR R9, =RAM_BASE ; Destination LDMIA R8!, {R0-R7} ; Load Vectors STMIA R9!, {R0-R7} ; Store Vectors LDMIA R8!, {R0-R7} ; Load Handler Addresses STMIA R9!, {R0-R7} ; Store Handler Addresses ENDIF

    ; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------

    MEMMAP EQU 0xE01FC040 ; Memory Mapping Control IF :DEF:REMAP LDR R0, =MEMMAP IF :DEF:EXTMEM_MODE MOV R1, #3 ELIF :DEF:RAM_MODE MOV R1, #2 ELSE MOV R1, #1 ENDIF STR R1, [R0] ENDIF

    ; Setup Stack for each mode ----------------------------------------------------

    LDR R0, =Stack_Top

    ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size

    ; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size

    ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size

    ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size

    ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size

    ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR IF :DEF:__MICROLIB

    EXPORT __initial_sp

    ELSE

    MOV SP, R0 SUB SL, SP, #USR_Stack_Size

    ENDIF

    ; Enter the C code -------------------------------------------------------------

    IMPORT __main LDR R0, =__main BX R0

    IF :DEF:__MICROLIB

    EXPORT __heap_base EXPORT __heap_limit

    ELSE
    ; User Initial Stack & Heap ALIGN 4 AREA |.text|, CODE, READONLY

    IMPORT __use_two_region_memory EXPORT __user_initial_stackheap

    __user_initial_stackheap

    LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + USR_Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDIF

    END

Reply
  • ; Copy Exception Vectors to Internal RAM ---------------------------------------

    IF :DEF:RAM_INTVEC ADR R8, Vectors ; Source LDR R9, =RAM_BASE ; Destination LDMIA R8!, {R0-R7} ; Load Vectors STMIA R9!, {R0-R7} ; Store Vectors LDMIA R8!, {R0-R7} ; Load Handler Addresses STMIA R9!, {R0-R7} ; Store Handler Addresses ENDIF

    ; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------

    MEMMAP EQU 0xE01FC040 ; Memory Mapping Control IF :DEF:REMAP LDR R0, =MEMMAP IF :DEF:EXTMEM_MODE MOV R1, #3 ELIF :DEF:RAM_MODE MOV R1, #2 ELSE MOV R1, #1 ENDIF STR R1, [R0] ENDIF

    ; Setup Stack for each mode ----------------------------------------------------

    LDR R0, =Stack_Top

    ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size

    ; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size

    ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size

    ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size

    ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size

    ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR IF :DEF:__MICROLIB

    EXPORT __initial_sp

    ELSE

    MOV SP, R0 SUB SL, SP, #USR_Stack_Size

    ENDIF

    ; Enter the C code -------------------------------------------------------------

    IMPORT __main LDR R0, =__main BX R0

    IF :DEF:__MICROLIB

    EXPORT __heap_base EXPORT __heap_limit

    ELSE
    ; User Initial Stack & Heap ALIGN 4 AREA |.text|, CODE, READONLY

    IMPORT __use_two_region_memory EXPORT __user_initial_stackheap

    __user_initial_stackheap

    LDR R0, = Heap_Mem LDR R1, = (Stack_Mem + USR_Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDIF

    END

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