Hello, Maybe somebody from Keil can explain this; I still haven't tried it on the device itself, but it would be refreshing to understand the actual requirements. Trying to run a STR9 at 96 MHz, I stubled upon the following guildelines:
KEIL (see http://www.keil.com/support/docs/3306.htm) When you set the PLL post-divider value (PLL_PDIV) to 2 (hence: in order to run at 96 MHz), you must change the Clock Control Register (SCU_CLKCNTR) to the following: * EMIRATIO: External Memory Interface Ratio fBCLK=HCLK/2 *
FMISEL: Flash Memory Interface Clock Divider FMICLK=RCLK/2
ST (see www.st.com/.../13563.pdf) The Flash memory interface clock (FMICLK) should have the same frequency as the RCLK clock (96 MHz)
this means no FMICLK dividers used
. As a result since Flash has a Sequential Burst read up to 96 MHz, we reduce execution time from there.
I have experienced blocked JTAG in some user codes I've received and they all configured the clock improperly (invalid values in registers or clocks not in specified boundaries).
I haven't investigated into details and I don't remember the exact values anymore which caused the problems. I just know that such HW problem exist and provided a solution for JTAG recovery (maybe newer silicon revisions have less such problems).
Also I haven't seen this documented by ST however it happens on HW.
Thanks a lot for your assistence.