We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello, Maybe somebody from Keil can explain this; I still haven't tried it on the device itself, but it would be refreshing to understand the actual requirements. Trying to run a STR9 at 96 MHz, I stubled upon the following guildelines:
KEIL (see http://www.keil.com/support/docs/3306.htm) When you set the PLL post-divider value (PLL_PDIV) to 2 (hence: in order to run at 96 MHz), you must change the Clock Control Register (SCU_CLKCNTR) to the following: * EMIRATIO: External Memory Interface Ratio fBCLK=HCLK/2 *
FMISEL: Flash Memory Interface Clock Divider FMICLK=RCLK/2
ST (see www.st.com/.../13563.pdf) The Flash memory interface clock (FMICLK) should have the same frequency as the RCLK clock (96 MHz)
this means no FMICLK dividers used
. As a result since Flash has a Sequential Burst read up to 96 MHz, we reduce execution time from there.