As far as I know, atomic operation are those which can not be interrupted. It implies that that they are single cycle operation. Because any operation having more than one cycle can be interrupted if any high priority interrupt comes.
Now bit or port pin manipulation in cortex M3 involves 3 instruction i.e load,move,store. So how can this be atomic, any high priority interrupt can occur after load or move instruction.
The Cortex-M3 supports "bit-band" accesses in hardware so the a single write from the core to s specific address can do a read-modify-write that sets or clears a single bit at a related address.
See also the Cortex-M3 TRM: www.keil.com/.../ddi0337i_cortexm3_r2p1_trm.pdf
and the __attribute__((bit band)) documentation: www.keil.com/.../armccref_babcbgfc.htm
With the bit banding - where every bit of the 32-bit word gets expanded into a full int in a separate memory region - the processor do not need to perform any load/modify/store to change the state of a single bit.
It can just perform a store - of zero or one - to an int-sized memory address. And the hardware in the peripherial device will merge in that bit.
So it is only when you need to play with multiple bits at the same time that you need a load/modify/store. And for that reason, a number of microcontrollers also have dedicated "set" and "clear" registers, that allows a single store, without any need for a load+update to set one or more bits, or to clear one or more bits, atomically with a single processor instruction.
Atomic operations against memory are rarely single cycle events.
There are many instructions that take multiple cycles, interrupts are simply deferred until the processor is in a state to accept them.
Using bit banding in peripheral space is very dangerous as the modification of registers is outside the view/control of the processor.
I should have been more clear: a single store to a bit-band alias address is atomic with respect to the processor because it is a single, uninterruptible instruction. In response the hardware will do a read-modify-write operation which will appear on the bus as one read cycle and one write cycle to the corresponding address in the bit-band region with the bus lock signal asserted (so the operation is also atomic on the bus).