As far as I know, atomic operation are those which can not be interrupted. It implies that that they are single cycle operation. Because any operation having more than one cycle can be interrupted if any high priority interrupt comes.
Now bit or port pin manipulation in cortex M3 involves 3 instruction i.e load,move,store. So how can this be atomic, any high priority interrupt can occur after load or move instruction.
Atomic operations against memory are rarely single cycle events.
There are many instructions that take multiple cycles, interrupts are simply deferred until the processor is in a state to accept them.
Using bit banding in peripheral space is very dangerous as the modification of registers is outside the view/control of the processor.