As far as I know, atomic operation are those which can not be interrupted. It implies that that they are single cycle operation. Because any operation having more than one cycle can be interrupted if any high priority interrupt comes.
Now bit or port pin manipulation in cortex M3 involves 3 instruction i.e load,move,store. So how can this be atomic, any high priority interrupt can occur after load or move instruction.
I should have been more clear: a single store to a bit-band alias address is atomic with respect to the processor because it is a single, uninterruptible instruction. In response the hardware will do a read-modify-write operation which will appear on the bus as one read cycle and one write cycle to the corresponding address in the bit-band region with the bus lock signal asserted (so the operation is also atomic on the bus).