we set CCLOCK to 60MHz, SSP0 divider is 2, so in lpc2300.s PCLKSEL1_Val should be 0x800.
// SSPCPSR clock prescale register, master mode, // minimum divisor is 0x02 SSP0CPSR = 0x06;
the clock freq. should be 60/2/6=5Mhz, but the measurement is 2.5MHz.
i checked SPI, calculation matches the measurement.
Do you have the experiences?
Thanks in advance
External crystal is 12MHz, M=20 N=1, PLL output freq. is 480MHz, CCLK is 60MHz CPU is LPC2366, IDE is uVision3 Debugger is uLink3
we use keil free RTL.
thanks for your help.
I managed to configure PLL output of 48MHz using the following settings: PLL multiply ration 16, N = 2, using a Xtal of 12 MHz, prescalar ration 1:2. are you sure you are running at 48 MHz?
Hello TP Liu,
maybe the problem is that the PLL output (FCCO) is limited to 290MHz. Please see errata sheet for LPC2366 on the NXP site www.standardics.nxp.com/.../errata.lpc2366.pdf
Best Regards, Martin Guenther
2x16x12/2=192MHz, Is PLL output 48MHz?
Thanks for your information, my cpu is Rev'A'device shouldn't be restricted by 299mhz.