we set CCLOCK to 60MHz, SSP0 divider is 2, so in lpc2300.s PCLKSEL1_Val should be 0x800.
// SSPCPSR clock prescale register, master mode, // minimum divisor is 0x02 SSP0CPSR = 0x06;
the clock freq. should be 60/2/6=5Mhz, but the measurement is 2.5MHz.
i checked SPI, calculation matches the measurement.
Do you have the experiences?
Thanks in advance
I managed to configure PLL output of 48MHz using the following settings: PLL multiply ration 16, N = 2, using a Xtal of 12 MHz, prescalar ration 1:2. are you sure you are running at 48 MHz?
2x16x12/2=192MHz, Is PLL output 48MHz?