Good day!
Can I get from C166/EC166 compilers information about all nested includes such as -M, -MM, -MD, -MMD keys for GCC compiler?
If not, I can only use make for rebuild target?
GNU make is case-sensitive so be careful with .OBJ, .obj, etc! Unless you have a special case-insensitive build of GNU make, see GNU make build instructions and Win32 specifics.
-- J
At first run I get .ic (rule with EC166) file and error with C166 rule
If you shows us the error(s) (copy/paste), we might be able to figure out what's happening.
They should! Check their output for any errors/warnings.
Yes, my compilers prints the some warnings... Should I supress this action?
My output... (first run after clean)
G:\##\Projects\Infineon XC167\ip++3>echo VSLICKERRORPATH="G:\##\Projects\Infineon XC167\ip++3" VSLICKERRORPATH="G:\##\Projects\Infineon XC167\ip++3" G:\##\Projects\Infineon XC167\ip++3>make.bat EC166 main.cpp MODV2 HCOMPACT INCDIR\(.\INC\;.\inc\uc_GUI\) EC166 EC++ COMPILER V1.09b COPYRIGHT KEIL ELEKTRONIK GmbH 2000 - 2006 EC166 COMPILATION COMPLETE. 3 WARNING(S), 0 ERROR(S) "MAIN.CPP", line 177: warning: variable "angle" was declared but never referenced ^ "MAIN.CPP", line 181: warning: variable "V_Rect" was declared but never referenced ^ "MAIN.CPP", line 185: warning: variable "VEL" was declared but never referenced ^ make: *** [main.ic] Error 1
The next question:
Do you use the Keil approach to make ".i, .ii, ..." file and use then like... C166 @filename
I want to make linker control file because there are many information in linker control string (CLASSES...) How can I make a dynamic control file for linker from "make"? (Windows)
P.S. EC++ is precompiler. it generates .ic files which contains auto generated C-code for further c-compilation.
Also check:
make -d make --debug=... make -p or make -qp
Check GNU make manual.
I've also added this to remove any existing GNU make defaults:
# ----------------------------------------------------- # CLEAR DEFAULT RULE # ----------------------------------------------------- .DEFAULT : # ----------------------------------------------------- # CLEAR SUFFIXES # ----------------------------------------------------- .SUFFIXES :
Quick hints (no time): - Link all objects to the final app.abs. - use a pattern rule to compile .c's or .ic's to .o's (see manual), example: %.o : *.c c166 etc.
%.o : *.ic [ if I understand EC166 correctly ] c166 etc.
- use a pattern rule to (pre)compile .cpp's to .ic's %.ic : %.cpp ec166 etc.
Also, make sure to use tabs in front of the commands. It's a bit "quircky" maybe but that's how GNU make works, but a common mistake to make.
No, you should fix the warnings :-)
Compile (CHECK TABS!):
$(OUTPUTDIR)/%.o : $(SOURCEDIR/%.c $(ECHO) "Compiling $< to" $(ECHO) " $@" $(ECHO) "$(call CONVERTPATH,$<)" > $(CMD_FILE) $(ECHO) "OBJECT($(call CONVERTPATH,$@))" >> $(CMD_FILE) $(ECHO) "PREPRINT($(call CONVERTPATH,$(@:.o=.i)))" >> $(CMD_FILE) $(ECHO) "PRINT($(call CONVERTPATH,$(@:.o=.lst)))" >> $(CMD_FILE) $(ECHO) "$(CCINCLUDES)" >> $(CMD_FILE) $(ECHO) "$(CCFLAGS)" >> $(CMD_FILE) $(ECHO) "$(CCDEFINES)" >> $(CMD_FILE) $(CC) @$(CMD_FILE) $(CCLOGFILE) $(ECHO) "Generating dependencies for $<..." $(MAKEDEPEND) $(call CONVERTPATH,$(@:.o=.i)) $@ > $(@:.o=.dep)
Link (CHECK TABS):
$(OUTPUTDIR)/APP.abs : $(OBJECTS) $(LINKERFILE) $(ECHO) "Linking the following files to $@" $(QUIET)FOR %%f in ( $(OBJECTS) ) DO $(ECHO) " %%f" $(ECHO) "$(call CONVERT_L166OBJECTS,$(OBJECTS))" > $(CMD_FILE) $(ECHO) "TO $(call CONVERTPATH,$@)" >> $(CMD_FILE) $(ECHO) "$(LDFLAGS)" >> $(CMD_FILE) $(CP) $(call CONVERTPATH,$(CMD_FILE)) + $(call CONVERTPATH,$(LINKERFILE)) $(call CONVERTPATH,$(CMD_FILE)) >NUL $(LD) @$(CMD_FILE) $(LDLOGFILE)
xxLOGFILE = "> cc.log" or "> ld.log" or something (optional) CONVERPATH does \ to / LINKERFILE = fixed part of linker command file (memory map, etc.)
The use of command files, depends on the shell you're using (CMD.exe, CygWin, etc.) and older Keil tools didn't handle long command lines very well. Maybe it's currently possible to do without the command files and @<file>, not sure.
Thank you!
Correction: CONVERPATH does \ to / should be / to \ I use / everywhere in GNU make.
Older Keil tools and some Win32 commands, didn't handle backslashes very well (??). Not the most beautiful solution, I agree, but it worked.
Older Keil tools and some Win32 commands, didn't handle backslashes very well (??).
-> forward slashes *sigh* :-)
Welcome. Let me know the results :-)
Hi Joost!
Please explain me following strings:
... $(OUTPUTDIR)/%.o : $(SOURCEDIR/%.c $(ECHO) "Compiling $< to" $(ECHO) " $@" $(ECHO) "$(call CONVERTPATH,$<)" > $(CMD_FILE) ...
What is $(call CONVERTPATH,$<)? CONVERTPATH is var or macros? Has it declaried earlier? I don't have experience in "make" & don't use call function... :)
I try to make this...
SOURCEDIR = G:\##\Projects\Infineon XC167\ip++3 OUTPUTDIR = $(SOURCEDIR) $(OUTPUTDIR)/%.o: $(SOURCEDIR)/%.cpp $(ECHO) "$(call CONVERTPATH,$<)" > c.txt
It not works. (Error 127)
See my earlier posts where I explained what CONVERTPATH does. But you're right, I didn't mention that it's not a built-in GNU make macro. I defined it myself because of some complaining tools. Definition:
# NOTE: do -not- use := to define a function; deferred expansion is needed. # # Function to convert forward slashes to backslashes # CONVERTPATH = $(subst /,\,$(strip $(1)))
Maybe you don't need CONVERTPATH at all. Try removing it. Even MS-DOS <3.x is supposed to support forward slashes but I still experienced problems with some tools. We changed some tools/versions in the meantime so maybe we don't need it anymore, haven't checked. 2008 and still messing with forward/backslashes :-/ Or should I say :-\ :-)
But do be careful with spaces in paths/filenames and add quotes where necessary.
I also suggest to only use forward or backslashes in your makefiles and don't mix them. I use forward slashes myself. Check your SOURCEDIR for example.
In your example, add an initial rule, for example (pseude code):
all: APPLICATION APPLICATION: APP.abs APP.abs : main.o fubar.o <L166 objects> $(OUTPUTDIR)/%.o: $(SOURCEDIR)/%.cpp <(E)C166 source files> etc...
Check GNU make manual for more info on $(call <macro>).
Oh, and $(ECHO) is a macro containing the Unix version of echo, not the Win32/CMD.exe built-in.
# cmd.exe's internal echo command is awful, using a better one. # Option -E = disable special (escaped) characters in strings (i.e. \t = tab) # # The executable was renamed to echo2.exe to prevent the internal cmd.exe # echo command from being used in case of typos. ECHO_PLAIN := $(PROJECT.TOOLSDIR)\unxutils\echo2 -E ECHO := $(QUIET)$(ECHO_PLAIN)
Good luck! J
ECHO := $(QUIET)$(ECHO_PLAIN)
What is QUIET? @? I attempt to use without any "QUIET" and have following trouble: echo2 (unix) doesn't print anything to file, but file creates and empty strings adds. (only from make!!) from cmd echo2 works good without any troubles, why?
this echo2 string good works from cmd, but not works from make:
[TAB]echo2 "any text" >> 1.dat
-E key don't care.
What is QUIET? @?
Yep. This way you can set/unset the QUIET macro in one place to do some debugging.
Works in cmd.exe but not in GNU make...? That's weird.
.PHONY: all all: [TAB]echo2 "this is a test" >> 1.dat
W:\>gmake -f test.mk echo2 "this is a test" >> 1.dat W:\>cat 1.dat this is a test W:\>gmake -v GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. This program built for Windows32 (HAVE_CASE_INSENSITIVE_FS) W:\> _
Working fine here. GNU make 3.81 .