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Is this possible if we use hard reset (Logic 1 Pulse with some delay) by using ISR and one Port Pin Connected to RESET Pin? so that Controller can RESET itself by Applying RESET signal by ISR. I mean Software *** Hardware RESET!
AT89S52 can be reset with logic high for 2 machine cycles to RESET PIN. I used Proteus VSM 7.1 and it shows RESET... Reset itself by ISR and Port Pin
delay(); RESET_Port_Pin=1; //Soft Reset to uC by Port Pin delay(); RESET_Port_Pin=0; delay();
But in Actual Circuit this Doesn't works. Without any chip it could be done or not? I think momentry latching of some type will help? Please help!
I can't imagine that working. The AT89S52 has a watchdog that can be enabled and then servicing of it ignored to cause a reset.
Thanx.. Plz tell me that Watchdog timer can be enabled in External Interrupt routine for within ISR only, or not?
An unconventional approach, but yes. Read your datasheet.
AT89S52 Datasheet shows that it supports Watchdog timer but uVision3's AT89X52 or REGX52.H file doesn't contain any SFR definitions for Watchdog timer. Datasheet is also not so clear that i can use Watchdog timer within ISR.
If you want to generate a RESET manually in your ISR,you could have others methodes,searching the old threads list.
The REGx52.h , AT89X52.h,and .etc are not supposed to have any extended SFRs than the standard Intel-8052 architecture been included. Otherwise,you the programmer should add them to the header files from Keil. If you do want to avoid this work(not dirty however),turn your browser to the chip manufacture's site for luck.
By the way,the watchdog will not help you generate a intended RESET.It generally give out unintended RESETs rather, which should be avoided...
"Datasheet is also not so clear that i can use Watchdog timer within ISR."
You can enable and then ignore servicing the watchdog from any context.
"By the way,the watchdog will not help you generate a intended RESET."
This is quite an unusual and surprising notion to those of us who have been using the watchdog to generate a reset.
Please elaborate how you have come to this conclusion!
"... you could have others methodes, searching the old threads list ... the watchdog will not help you generate a intended RESET"
On the contrary - searching the "old threads list" most certainly will reveal plenty of recommendations to use the Watchdog for exactly this purpose!!
"watchdog will ... generally give out unintended RESETs rather, which should be avoided"
If that is your experience of watchdogs, then you have not been using them correctly!
"The REGx52.h , AT89X52.h,and .etc are not supposed to have any extended SFRs than the standard Intel-8052 architecture been included."
The header recommended for the AT89S52 is REGX51.h: http://www.keil.com/dd/chip/3411.htm
The comment at the top of REGX51.H says,
//*------------------------------------------------------------------------- AT89X51.H (sic) Header file for the low voltage Flash Atmel AT89C51 and AT89LV51. Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc. All rights reserved. --------------------------------------------------------------------------*/
http://www.keil.com/dd/docs/c51/atmel/regx51.h
so you're right - nothing specific to the AT89S52
The comment at the top of AT89X52.H also says,
/*-------------------------------------------------------------------------- AT89X52.H Header file for the low voltage Flash Atmel AT89C52 and AT89LV52. Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc. All rights reserved. --------------------------------------------------------------------------*/
http://www.keil.com/dd/docs/c51/atmel/AT89X52.h
Again, nothing specific to the AT89S52.
So it looks like Keil's recommendation is a bit dodgy!
But, as you say, there's nothing to stop you adding the required definitions yourself; or take a look through the supplied Keil headers to see if you can find a better fit; or see if Atmel has one...
Thank you Dan, Andy !! If you don't mind please provide one example of usage of Watchdog timer within ISR, Special SFR for Watchdog timer is WDTRST (0xA6) and WDTPRG (0xA7). I didn't used WDT earlier. Please..
Datasheet Describes...... The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDT.... To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register.
IE = 0; WDTRST = 0x1E; WDTRST = 0xE1; for (;;);
Oops, different processor.
s/IE/EA/
Actually I had tried that
WDTRST = 0x1E; WDTRST = 0xE1; while(1);
but it didn't worked. nothing happens with RESET by ISR (Only some port reset as it have to do).
I think i will have to do some hit and trial for this.
Actually uC is in while(1) loop and WDT doesn't overflows to cause a reset.
How WDT will cause Overflow in that routine so that it can RESET uC AT89S52. i think it will take 16ms approx for 11.0592MHz, but it is still in while loop?
Thanx again Dan Henry!
Did you find WDTRST defined in your processor-specific header file or did you add it yourself?
How is WDTRST defined?