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Is this possible if we use hard reset (Logic 1 Pulse with some delay) by using ISR and one Port Pin Connected to RESET Pin? so that Controller can RESET itself by Applying RESET signal by ISR. I mean Software *** Hardware RESET!
AT89S52 can be reset with logic high for 2 machine cycles to RESET PIN. I used Proteus VSM 7.1 and it shows RESET... Reset itself by ISR and Port Pin
delay(); RESET_Port_Pin=1; //Soft Reset to uC by Port Pin delay(); RESET_Port_Pin=0; delay();
But in Actual Circuit this Doesn't works. Without any chip it could be done or not? I think momentry latching of some type will help? Please help!
Thank you Dan, Andy !! If you don't mind please provide one example of usage of Watchdog timer within ISR, Special SFR for Watchdog timer is WDTRST (0xA6) and WDTPRG (0xA7). I didn't used WDT earlier. Please..
Datasheet Describes...... The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDT.... To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register.
IE = 0; WDTRST = 0x1E; WDTRST = 0xE1; for (;;);
Oops, different processor.
s/IE/EA/
Actually I had tried that
WDTRST = 0x1E; WDTRST = 0xE1; while(1);
but it didn't worked. nothing happens with RESET by ISR (Only some port reset as it have to do).
I think i will have to do some hit and trial for this.
Actually uC is in while(1) loop and WDT doesn't overflows to cause a reset.
How WDT will cause Overflow in that routine so that it can RESET uC AT89S52. i think it will take 16ms approx for 11.0592MHz, but it is still in while loop?
Thanx again Dan Henry!
Did you find WDTRST defined in your processor-specific header file or did you add it yourself?
How is WDTRST defined?
i had to add... sfr WDTRST = 0xA6;
Andy,Dan,do you mean that write a near-to-overflow value to the watchdog and it will generate a RESET?
If so,I was really in faulty using.
"do you mean that write a near-to-overflow value to the watchdog and it will generate a RESET?"
Not necessarily.
If you enable the watchdog and then deliberately do not service it, it will generate a Reset!
As Dan showed:
IE = 0; WDTRST = 0x1E; // Enable the watchdog WDTRST = 0xE1; for (;;); // Infinite loop
That is its job, after all!
"sfr WDTRST = 0xA6;"
That's what it should be and the watchdog start sequence is the same provided by Atmel in their code samples. I didn't find any errata. The compiler should be emitting the following:
C2AF CLR EA 75A61E MOV WDTRST,#01EH 75A6E1 MOV WDTRST,#0E1H
What I learned was the controller would run into unknown states, for both hardware and software reasons.So the programmers enable the watchdog in the initial section and feed it every intervals.Hence once the controller flies away or stays long in unintended loop,the Watchdog would compliant for the ignoring. So the controller will be reset.
Is the usage above of faulty?
"Is the usage above of faulty?"
No, in fact, that usage model is the convention.
James hopes to use the watchdog in a less conventional way to programmatically cause a reset by enabling it and then not servicing it so that the watchdog timer expires and generates a reset.
"Hence once the controller flies away or stays long in unintended loop,the Watchdog would compliant for the ignoring. So the controller will be reset."
Exactly!
And so, if you deliberately don't service the watchdog, you know that it will cause a reset!
QEF.
I am, in fact, using the watchdog both ways in the same project.
Erik
Thanx to all Dan,Andy,Erik. WDT worked very well in ISR as provided by DAN HENRY (Special Thanks) >Ninja Z misguiding us.<
I had some problem in Circuit and now it's fully working. Actually i wanted a reset without Port High as RESET button pressed for long time does. This ISR causes RESET of uC without Ports High.
Again thanx to DAN HENRY for so much help.