Hi,
could someone give me some advice to build another dataflash algorithm to download code via jtag to the dataflash connected at the spi interface (for the AT91RM9200 controller).
I just take a look into the AT91SAM9_DF_P1056_CS0 file, but I don't know where I can get the "Run User Programs After Build / Rebuild" (Options-for-target->User) flx-file.
And is it right, that I have to choose the internal RAM for the ROM definitions under options-for-target->Target, too?
best regards Hans
thanks for your answer. I just take a look at the blinky AT91SAM9260 example, which uses the spi dataflash. There's a version where the code is loaded into the internal RAM which is only 4k - the internal RAM from the AT91RM9200 is 16k...
I started a new project which includes only a while(1) loop - nothing else. So I get the error "Insufficient RAM for flash Algorithm!" . But how should such a really small example work with the SAM9260 (with only 4k internal RAM)???
And the scatter-file is nearly the same one
; ************************************************************* ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* LR_IROM1 0x00000000 0x00001000 { ; load region size_region ER_IROM1 0x00000000 0x00001000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } RW_IRAM1 0x00300000 0x00001000 { ; RW data .ANY (+RW +ZI) } }
I also include the RAM.ini with the correct register and values for the AT91RM9200...
FUNC void Setup (void) { // <o> Program Entry Point PC = 0x00000000; } // Switching from Slow Clock to Main Oscillator for faster Download _WDWORD(0xFFFFFC20, 0x00000601); // PMC_MOR: Enable Main Oscillator _sleep_(10); // Wait for stable Main Oscillator _WDWORD(0xFFFFFC30, 0x00000001); // PMC_MCKR: Switch to Main Oscillator _WDWORD(0xFFFFFD08, 0x00010000); // WDT_MR: Disable Watchdog _WDWORD(0xFFFFFF00, 0x00000001); // MATRIX_MRCR: Remap IRAM to 0 (for RM9200) Setup(); // Init, and setup for Running LOAD easytest.axf INCREMENTAL // Download g, main
What about this line (in the example when I use only the internal RAM)?
#define SDRAM_START 0x20000000
If I understand you right, then this line is only correct, when I download the code from the jtag interface to the SDRAM, where the code is executed to install the spi connection (to store the ROM values in the dataflash).
At the moment I only want to test the dataflash (I don't have any SDRAMs installed) to see that it works fine (with a small example - only to turn on a led)...
The test project which you have built will not cause the message "Insufficient RAM for Flash Algorithm!". This will be caused by your Data Flash Algorithm which is not written properly (all algorithms in the Keil installation use far less then 4kB of memory).
You should look at the chips manual to see from which memories you can execute code. Since you have no SDRAM and probably no other external RAM or Flash (except SPI Data Flash) then you can execute code only from internal RAM (16kB). This limits your application to 16kB in size. You can still use the Data Flash to make the code bootable but you can't execute code directly from SPI Data Flash (it needs to be downloaded into RAM first as already described).
all algorithms in the Keil installation use far less then 4kB of memory
When I right, then I have to download the dataflash algorithm (first) in the internal RAM to enable the spi controller (and the spi connection).
RAM Size = RW Data + ZI Data = 12 + 132 ROM Size = Code + RO Data + RW Data = 1948 + 4256 + 12
But I found my error for this error message (I forgot to change the RAM size in the uvision project (within the Flash Download Setup window).
So now the software told me that there are no errors during the download to the spi dataflash. But when I try to start the programm, then I get a error messages (within the registers) access violation at 0xFFFFFFFC for example. These errors occured when I run the startup-script.
I don't think that the write progress is successful - because when I restart the processor no data will be transmitted to the processor from the dataflash - there's only one short peak (when the processors searchs for a valid sequence).
Within the FlashPrg.c file: I use the start addr from the internal RAM for
#define SDRAM_START
and the offset is 0xE00.
I'm sitting in front of the data flash code but I don't see the error / responsible for the errors.
Reinhard, could you give me a example for the AT91RM9200 together with the AT45DB021B data flash from Atmel? I've only the internal RAM from the controller to test the data flash.
Send your projects (Data Flash algorithm and example application) with detailed description of the problem to support.intl@keil.com