Hello,
I have another question about the AT91RM9200... I want to configurate the startup file to be able to use the gnu compiler.
Therefore I took a look into the startup file for one gnu example - there is no definition of the heap - is that correct?
What are the differences between the startup files (using gnu or using realview compiler)? Is it correct to change only the order by the configuration of the PIO controller and the mode bits?
.equ Mode_USR 0x10
Where do I have to configurate the memory configuration in the gnu mode? When I use realview I can easily configurate the addresses where the internal / external ram /rom is - how is that possible with the gnu compiler? Because there's no such a field under "options for target" -> target?
best regards Johannes
so now I have only 50 errors - not 400 erros at the start
1.error: bad instruction 'preserve8'
;// <e> Instruction Cache Enable ;// </e> */ .equ CACHE_SETUP, 1 PRESERVE8
Should I delete this part of code - I didn't find the instruction cache in the other startup script.
2. error bad instruction area, RESET, CODE
# Startup Code must be linked first at Address at which it expects to run. AREA RESET, CODE, READONLY ARM _startup:
Is it correct to use here
# Starupt Code must be linked first at Address at which it expects to run. .text .arm .global _startup .func _startup _startup:
3. error bad instruction export reset handler
# Reset Handler EXPORT Reset_Handler Reset_Handler
Should I delete this part of the startup script to use it with the gnu compiler?
Moreover I have several errors in the part of the "setup external bus interface (EBI)", "setup power management controller" - I don't want to post everything - maybe anybody could tell what I've to do with this part of startup script.
now I try to load code to my at91rm9200 controller - but I get a error message
"no algorithm found for: 00008000H - 0000AB6FH" "Erase skipped!"
Under Options for Target->Utilities->Settings I changed nothing, because it works with the realview compiler... And when I changed the programming algorithm then I got the same error message.
Could there be something wrong with the staartup file, I created for the GNU compiler?
linking... /cygdrive/c/Cygnus/Arm-Tools/Bin/../lib/gcc-lib/arm-thumb-elf/3.3.1/../../../../arm-thumb-elf/bin/ld: gnutest.elf: Not enough room for program headers, try linking with -N /cygdrive/c/Cygnus/Arm-Tools/Bin/../lib/gcc-lib/arm-thumb-elf/3.3.1/../../../../arm-thumb-elf/bin/ld: final link failed: Bad value collect2: ld returned 1 exit status Target not created
So I get new errors in the linker script; I use the one in the GNU folder from Keil and changed only the Memory Data and Memory Code...
MEMORY { CODE (rx) : ORIGIN = 0x10000000, LENGTH = 0x00FFFFFF /* external flash */ DATA (rw) : ORIGIN = 0x00000000, LENGTH = 0x000FFFFF /* internal SRAM */ }
The only think I found in the www is that, there could be a problem with the SIZEOF parameter in the linker script - but I don't find such parameter
Johannes
now I'm able to write code to my controller - but the code don't work...
there must be errors in the startup file I created for the GNU compiler. When I run in debug mode, I see only many assembler codes (no comments as it is when I work with the realview compiler)
the last line is: 0x00200000 EAFFFFFE DD 0xEAFFFFE
after this line nothing happens...
Is there anybody who works with this AT91RM9200 controller and with the gnu compiler?
here is the part of the startup file, where the error must be.
/* ;// <e> External Bus Interface (EBI) */ .equ EBI_SETUP, 1 .equ SMC_CSR0_SETUP, 0x00000001 .equ SMC_CSR0_Val, 0x00003284 .equ SMC_CSR1_SETUP, 0x00000000 .equ SMC_CSR1_Val, 0x00000000 .equ SMC_CSR2_SETUP, 0x00000000 .equ SMC_CSR2_Val, 0x00000000 .equ SMC_CSR3_SETUP, 0x00000000 .equ SMC_CSR3_Val, 0x00000000 .equ SMC_CSR4_SETUP, 0x00000000 .equ SMC_CSR4_Val, 0x00000000 .equ SMC_CSR5_SETUP, 0x00000000 .equ SMC_CSR5_Val, 0x00000000 .equ SMC_CSR6_SETUP, 0x00000000 .equ SMC_CSR6_Val, 0x00000000 .equ SMC_CSR7_SETUP, 0x00000000 .equ SMC_CSR7_Val, 0x00000000 .equ EBI_CFG_SETUP, 0x00000001 .equ EBI_CSA_Val, 0x00000002 .equ EBI_CFGR_Val, 0x00000000 /* ;// <e> SDRAM Controller (SDRAMC) */ .equ SDRAMC_SETUP, 1 .equ SDRAMC_MR_Val, 0x00000000 .equ SDRAMC_TR_Val, 0x000002E0 .equ SDRAMC_CR_Val, 0x2188C155 .equ SDRAMC_SRR_Val, 0x00001955 .equ SDRAMC_IER_Val, 0x00000000 .equ BFC_SETUP, 0 .equ BFC_MR_Val, 0x00000000 # Power Management Controller (PMC) definitions .equ PMC_BASE, 0xFFFFFC00 /* PMC Base Address */ .equ PMC_SCER_OFS, 0x00 /* Sys Clk Enable Reg Address Offset */ .equ PMC_SCDR_OFS, 0x04 /* Sys Clk Disable Reg Address Offset */ .equ PMC_SCSR_OFS, 0x08 /* Sys Clk Status Reg Address Offset */ .equ PMC_PCER_OFS, 0x10 /* Periph Clk Enable Reg Address Offset */ .equ PMC_PCDR_OFS, 0x14 /* Periph Clk Disable Reg Address Offset */ .equ PMC_PCSR_OFS, 0x18 /* Periph Clk Status Reg Address Offset */ .equ CKGR_MOR_OFS, 0x20 /* Main Oscillator Reg Address Offset */ .equ CKGR_MCFR_OFS, 0x24 /* Main Clock Freq Reg Address Offset */ .equ CKGR_PLLAR_OFS, 0x28 /* PLLA Reg Address Offset */ .equ CKGR_PLLBR_OFS, 0x2C /* PLLA Reg Address Offset */ .equ PMC_MCKR_OFS, 0x30 /* Master Clock Reg Address Offset */ .equ PMC_PCK0_OFS, 0x40 /* Programmable Clk 0 Reg Address Offset */ .equ PMC_PCK1_OFS, 0x44 /* Programmable Clk 1 Reg Address Offset */ .equ PMC_PCK2_OFS, 0x48 /* Programmable Clk 2 Reg Address Offset */ .equ PMC_PCK3_OFS, 0x4C /* Programmable Clk 3 Reg Address Offset */ .equ PMC_IER_OFS, 0x60 /* Interrupt Enable Reg Address Offset */ .equ PMC_IDR_OFS, 0x64 /* Interrupt Disable Reg Address Offset */ .equ PMC_SR_OFS, 0x68 /* Status Reg Address Offset */ .equ PMC_IMR_OFS, 0x6C /* Interrupt Mask Reg Address Offset */ /* ; Bit constants */ .equ PMC_MOSCEN, (1<<0) /* Main Oscillator Enable */ .equ PMC_MUL, (0x7FF<<16) /* PLL Multiplier */ .equ PMC_MOSCS, (1<<0) /* Main Oscillator Stable */ .equ PMC_LOCKA, (1<<1) /* PLL A Lock Status */ .equ PMC_LOCKB, (1<<2) /* PLL A Lock Status */ .equ PMC_MCKRDY, (1<<3) /* Master Clock Status */ .equ PMC_SETUP, 1 .equ PMC_SCER_Val, 0x00000001 .equ PMC_PCER_Val, 0x00000018 .equ CKGR_MOR_Val, 0x0000FF01 .equ CKGR_PLLAR_Val, 0x2026BF04 .equ CKGR_PLLBR_Val, 0x10483F0E .equ PMC_MCKR_Val, 0x00000202 .equ PMC_PCK0_Val, 0x00000000 .equ PMC_PCK1_Val, 0x00000000 .equ PMC_PCK2_Val, 0x00000000 .equ PMC_PCK3_Val, 0x00000000 /* ; Area Definition and Entry Point */ # Startup Code must be linked first at Address at which it expects to run. .text .arm .global _startup .func _startup _startup: # Exception Vectors # Mapped to Address 0. # Absolute addressing mode must be used. # Dummy Handlers are implemented as infinite loops which can be modified. Vectors: LDR PC,Reset_Addr LDR PC,Undef_Addr LDR PC,SWI_Addr LDR PC,PAbt_Addr LDR PC,DAbt_Addr NOP /* Reserved Vector */ # LDR PC, IRQ_Addr LDR PC, [PC, #-0xF20] /* Vector from AIC_IVR */ # LDR PC, FIQ_Addr LDR PC, [PC, #-0xF20] /* Vector from AIC_FVR */ Reset_Addr: .word Soft_Reset Undef_Addr: .word Undef_Handler SWI_Addr: .word SWI_Handler PAbt_Addr: .word PAbt_Handler DAbt_Addr: .word DAbt_Handler .word 0 /* Reserved Address */ IRQ_Addr: .word IRQ_Handler FIQ_Addr: .word FIQ_Handler Soft_Reset: B Soft_Reset Undef_Handler: B Undef_Handler SWI_Handler: B SWI_Handler PAbt_Handler: B PAbt_Handler DAbt_Handler: B DAbt_Handler IRQ_Handler: B IRQ_Handler FIQ_Handler: B FIQ_Handler # Reset Handler Reset_Handler:
second part
.if PMC_SETUP # Setup System Clock LDR R0, =PMC_BASE /* ; System Clock Enable */ LDR R1, =PMC_SCER_Val STR R1, [R0, #PMC_SCER_OFS] /* ; Peripheral Clock Enable */ LDR R1, =PMC_PCER_Val STR R1, [R0, #PMC_PCER_OFS] .if CKGR_MOR_Val & PMC_MOSCEN /* ; Setup Main Oscillator */ LDR R1, =CKGR_MOR_Val STR R1, [R0, #CKGR_MOR_OFS] /* ; Wait until Main Oscillator is stabilized */ MOSCS_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_MOSCS BEQ MOSCS_Loop .endif .if CKGR_PLLAR_Val & PMC_MUL /* ; Setup the PLL A */ /* IF (CKGR_PLLAR_Val:AND:PMC_MUL) != 0 */ LDR R1, =CKGR_PLLAR_Val STR R1, [R0, #CKGR_PLLAR_OFS] /* ; Wait until PLL A is stabilized */ PLLA_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_LOCKA BEQ PLLA_Loop .endif .if CKGR_PLLBR_Val & PMC_MUL /* ; Setup the PLL B */ /* IF (CKGR_PLLBR_Val:AND:PMC_MUL) != 0 */ LDR R1, =CKGR_PLLBR_Val STR R1, [R0, #CKGR_PLLBR_OFS] /* ; Wait until PLL B is stabilized */ PLLB_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_LOCKB BEQ PLLB_Loop .endif /* ; Setup the Master Clock and the Processor Clock */ LDR R1, =PMC_MCKR_Val STR R1, [R0, #PMC_MCKR_OFS] /* ; Wait until Main Master Clock is ready */ MCKR_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_MCKRDY BEQ MCKR_Loop /* ; Setup Programmable Clock Register 0 */ LDR R1, =PMC_PCK0_Val STR R1, [R0, #PMC_PCK0_OFS] /* ; Setup Programmable Clock Register 1 */ LDR R1, =PMC_PCK1_Val STR R1, [R0, #PMC_PCK1_OFS] /* ; Setup Programmable Clock Register 2 */ LDR R1, =PMC_PCK2_Val STR R1, [R0, #PMC_PCK2_OFS] /* ; Setup Programmable Clock Register 3 */ LDR R1, =PMC_PCK3_Val STR R1, [R0, #PMC_PCK3_OFS] .endif # Copy Exception Vectors to Internal RAM SUB R8, PC, #.-Vectors+8 .ifdef REMAPPED MOV R9, #RAM_Base .else MOV R9, #RAM_Base_Boot .endif /* IF :DEF:RAM_INTVEC */ /* ADR R8, Vectors ; Source */ /* LDR R9, =RAM_BASE ; Destination */ LDMIA R8!, {R0-R7} /*; Load Vectors */ STMIA R9!, {R0-R7} /*; Store Vectors */ LDMIA R8!, {R0-R7} /*; Load Handler Addresses */ STMIA R9!, {R0-R7} /*; Store Handler Addresses */ /* ENDIF */ /* ; Remap on-chip RAM to address 0 */ /* IF :DEF:REMAP LDR R0, =MC_BASE MOV R1, #1 STR R1, [R0, #MC_RCR_OFS] ; Remap ENDIF */ # Initialise EBI and execute Remap LDR R12, AfterRemapAdr /* Get the Real Jump Address */ ADD R11, PC, #EBI_Table-.-8 LDMIA R11, {R0-R10} /* Load EBI Data */ STMIA R10, {R0-R9} /* Store EBI Data with Remap */ MOV PC, R12 /* Jump and flush Pipeline */ AfterRemapAdr: .word AfterRemap AfterRemap: # Initialise Interrupt System # ...