Hello,
I have another question about the AT91RM9200... I want to configurate the startup file to be able to use the gnu compiler.
Therefore I took a look into the startup file for one gnu example - there is no definition of the heap - is that correct?
What are the differences between the startup files (using gnu or using realview compiler)? Is it correct to change only the order by the configuration of the PIO controller and the mode bits?
.equ Mode_USR 0x10
Where do I have to configurate the memory configuration in the gnu mode? When I use realview I can easily configurate the addresses where the internal / external ram /rom is - how is that possible with the gnu compiler? Because there's no such a field under "options for target" -> target?
best regards Johannes
second part
.if PMC_SETUP # Setup System Clock LDR R0, =PMC_BASE /* ; System Clock Enable */ LDR R1, =PMC_SCER_Val STR R1, [R0, #PMC_SCER_OFS] /* ; Peripheral Clock Enable */ LDR R1, =PMC_PCER_Val STR R1, [R0, #PMC_PCER_OFS] .if CKGR_MOR_Val & PMC_MOSCEN /* ; Setup Main Oscillator */ LDR R1, =CKGR_MOR_Val STR R1, [R0, #CKGR_MOR_OFS] /* ; Wait until Main Oscillator is stabilized */ MOSCS_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_MOSCS BEQ MOSCS_Loop .endif .if CKGR_PLLAR_Val & PMC_MUL /* ; Setup the PLL A */ /* IF (CKGR_PLLAR_Val:AND:PMC_MUL) != 0 */ LDR R1, =CKGR_PLLAR_Val STR R1, [R0, #CKGR_PLLAR_OFS] /* ; Wait until PLL A is stabilized */ PLLA_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_LOCKA BEQ PLLA_Loop .endif .if CKGR_PLLBR_Val & PMC_MUL /* ; Setup the PLL B */ /* IF (CKGR_PLLBR_Val:AND:PMC_MUL) != 0 */ LDR R1, =CKGR_PLLBR_Val STR R1, [R0, #CKGR_PLLBR_OFS] /* ; Wait until PLL B is stabilized */ PLLB_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_LOCKB BEQ PLLB_Loop .endif /* ; Setup the Master Clock and the Processor Clock */ LDR R1, =PMC_MCKR_Val STR R1, [R0, #PMC_MCKR_OFS] /* ; Wait until Main Master Clock is ready */ MCKR_Loop: LDR R2, [R0, #PMC_SR_OFS] ANDS R2, R2, #PMC_MCKRDY BEQ MCKR_Loop /* ; Setup Programmable Clock Register 0 */ LDR R1, =PMC_PCK0_Val STR R1, [R0, #PMC_PCK0_OFS] /* ; Setup Programmable Clock Register 1 */ LDR R1, =PMC_PCK1_Val STR R1, [R0, #PMC_PCK1_OFS] /* ; Setup Programmable Clock Register 2 */ LDR R1, =PMC_PCK2_Val STR R1, [R0, #PMC_PCK2_OFS] /* ; Setup Programmable Clock Register 3 */ LDR R1, =PMC_PCK3_Val STR R1, [R0, #PMC_PCK3_OFS] .endif # Copy Exception Vectors to Internal RAM SUB R8, PC, #.-Vectors+8 .ifdef REMAPPED MOV R9, #RAM_Base .else MOV R9, #RAM_Base_Boot .endif /* IF :DEF:RAM_INTVEC */ /* ADR R8, Vectors ; Source */ /* LDR R9, =RAM_BASE ; Destination */ LDMIA R8!, {R0-R7} /*; Load Vectors */ STMIA R9!, {R0-R7} /*; Store Vectors */ LDMIA R8!, {R0-R7} /*; Load Handler Addresses */ STMIA R9!, {R0-R7} /*; Store Handler Addresses */ /* ENDIF */ /* ; Remap on-chip RAM to address 0 */ /* IF :DEF:REMAP LDR R0, =MC_BASE MOV R1, #1 STR R1, [R0, #MC_RCR_OFS] ; Remap ENDIF */ # Initialise EBI and execute Remap LDR R12, AfterRemapAdr /* Get the Real Jump Address */ ADD R11, PC, #EBI_Table-.-8 LDMIA R11, {R0-R10} /* Load EBI Data */ STMIA R10, {R0-R9} /* Store EBI Data with Remap */ MOV PC, R12 /* Jump and flush Pipeline */ AfterRemapAdr: .word AfterRemap AfterRemap: # Initialise Interrupt System # ...