Hello,
I need to know the exact number of the clock cycles per each instruction in terms of the system clock frequency especially the "LDR" instruction
Here is the needed instruction: "LDR r3,[r1]"
Note that r1 is an address in the timer peripheral which corresponds to the current timer value.
I found out that in this link: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/CHDCICDF.html
LDR instruction takes two cycles.
However, I measured the number of clock cycles taken in this instruction and i found that this instruction takes 2 clock cycles but not from system clock frequency. The 2 clock cycles are taken from the BUS clock frequency which the timer works by.
I have two questions for the sake of this behavior:
1- Is that normal that the LDR instruction takes the two clock cycles measured by the BUS frequency not the system clock frequency which the CPU works by ?
2- Is there a solid reference showing the number of clock cycles per instruction for ARM v6-M cortex M0 please ?
Thank you in advance.
The reference you linked says "The cycle counts are based on a system with zero wait-states." To me, that means "bus clock == cpu/system clock."Things on the other side of a bus, with different clock frequencies, could have "arbitrary" synchronization delays and similar, so it's difficult to figure out deterministic timings - they're vendor specific, for one thing.
As an example, an Atmel SAMD21 manual says:
13.3.1.8 Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
5⋅PGCLK +2⋅PAPB < D < 6⋅PGCLK +3⋅PAPB Where PGCLK is the period of the generic clock and PAPB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2⋅PAPB .