why the inter-core SGI interrupt cannot be trigged on GICv3 hardware

My hareware environment:

1.  a ARMv8 processor , which  runs in 64bit EL3 and 32bit EL2&EL1.

2. a GICv3 interrupt controller

Running in 32bit hyp mode,  I try to send a SGI interrupt from core0 to core1, but core1 cannot receive this interrupt. Below are what I've tried.

1. I use ICC_SGI1R to send the interrupt. GICD_SGIR cannot be used because "affinity routing" is enabled.

2. Group0, Group1NS and Group1S interrupt are enabled in GICD_CTLR

3. Write GICR_ISENABLER0 to enable SGI interrupt

4. The IRQ/FIQ are unmasked in core1's cpsr
5. Group1 intersuprt is enabled in core1's ICC_IGRPEN1 register

But after writting to  ICC_SGI1R, I can not find valid bit in pending state register, and core1's ICC_IAR register are also always invalid.

Do you have any suggestions with this issue?

Thanks in advance.

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  • moonlight wrote:

    Did you also write GICR_IGROUPR0 to set the interrupt as NS.G1?  (Note, you'll need to do this in Secure state)

    - No, I didn't, because the core is running in 32 bit hyp mode.  But, even so, if everyghing is ok, core 1 will receive a SGI either in group0 or group1, actually core1 see nothing.

    The sender indicates the Group (G0, S.G1, NS.G1) of interrupt it wants to send by which SGI register it writes.  The Group the sender specified has to match how the receiver(s) have configured that interrupt in their GICR_IGROUPR0/GICR_IGRPMODR0 registers.  If they don't, no interrupt is generated.

    Take a look at Table 11 in the GICv3 app note for a fuller explanation:

    GICv3 Software Overview

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  • moonlight wrote:

    Did you also write GICR_IGROUPR0 to set the interrupt as NS.G1?  (Note, you'll need to do this in Secure state)

    - No, I didn't, because the core is running in 32 bit hyp mode.  But, even so, if everyghing is ok, core 1 will receive a SGI either in group0 or group1, actually core1 see nothing.

    The sender indicates the Group (G0, S.G1, NS.G1) of interrupt it wants to send by which SGI register it writes.  The Group the sender specified has to match how the receiver(s) have configured that interrupt in their GICR_IGROUPR0/GICR_IGRPMODR0 registers.  If they don't, no interrupt is generated.

    Take a look at Table 11 in the GICv3 app note for a fuller explanation:

    GICv3 Software Overview

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