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Hi,
In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.
My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require the assertion of WLAST", how should I correctly understand this statement?
My understanding by intuition is that "WVALID should be asserted after WLAST was asserted", but it conflicts to my understanding of AXI signal dependency, or should I interpret "Dependencies on the assertion of WVALID" as BVALID signal?
Thanks.