Juno MMU setup

Hi,

2) Set TCR_EL2 with value (0x80923518) where  T0SZ=24, IRGN0=01, ORGN0=01,SH0=11,TG0=4K granule and PS=40 bits. (I get "Bus error" at this stage)

This is almost certainly caused by the MMU already being on at the point that you write to TCR_EL2, which in your case is resulting in a virtual address being translated to an invalid physical address because TTBR0_EL2 hasn't been set to the correct value yet. At the entry point to your program, please can you do this to ensure that the MMU is turned off:

LDR X0, =0x30C50830

MSR SCTLR_EL2, X0

This will safely disable the MMU and caches at EL2 while reserving SCTLR_EL2's RES1 bits.

Yes first entry for L0 table is = ((L1 page table address & 0xfffffffffffff000) | 0x3 ) similar for other block descriptors.

This is not the correct way to generate a table descriptor. From the ARMv8-A Architecture Reference Manual (DDI 0487A.f) section D4.4.1, the table descriptor at 4KB granularity expects bits [47:m] to be bits [47:m] of the next-level table's physical address. Bits [63:48] of the table descriptor include RES0 bits, some ignored bits, and some table attribute bits such as NSTable, APTable, XNTable, and PXNTable. The code you are using to generate your table descriptor is setting all of these bits to 1, including the RES0 bits [51:48].

Ash.

Hi,

2) Set TCR_EL2 with value (0x80923518) where  T0SZ=24, IRGN0=01, ORGN0=01,SH0=11,TG0=4K granule and PS=40 bits. (I get "Bus error" at this stage)

This is almost certainly caused by the MMU already being on at the point that you write to TCR_EL2, which in your case is resulting in a virtual address being translated to an invalid physical address because TTBR0_EL2 hasn't been set to the correct value yet. At the entry point to your program, please can you do this to ensure that the MMU is turned off:

LDR X0, =0x30C50830

MSR SCTLR_EL2, X0

This will safely disable the MMU and caches at EL2 while reserving SCTLR_EL2's RES1 bits.

Yes first entry for L0 table is = ((L1 page table address & 0xfffffffffffff000) | 0x3 ) similar for other block descriptors.

This is not the correct way to generate a table descriptor. From the ARMv8-A Architecture Reference Manual (DDI 0487A.f) section D4.4.1, the table descriptor at 4KB granularity expects bits [47:m] to be bits [47:m] of the next-level table's physical address. Bits [63:48] of the table descriptor include RES0 bits, some ignored bits, and some table attribute bits such as NSTable, APTable, XNTable, and PXNTable. The code you are using to generate your table descriptor is setting all of these bits to 1, including the RES0 bits [51:48].

Ash.

Hi Ash,

I am getting another issue when I setup my stage 2 page tables. I am again configuring for 40bit address range with VTCR_EL2 (T0SZ=24, TG0=00, SL0 = 2(starting at L0), PS=40bits ).

I am again getting "Bus error on memory operation" when I try to got to Guest VM memory even though my stage 2 translation tables are correct (I am mapping EL1 space pages and setting up stage 2 translations) which I verified using DS-5.

I also made sure that EL1 stage 1 translation is disabled and MMU is disabled by setting (SCTLR_EL1 = 0x30D00800).

I am getting issue when I tried to do "eret" to EL1 from EL2 mode. Please let me know what I am doing wrong ?

Thanks.