Juno MMU setup

Hi Martin,

Thanks. I also had understanding that PA range independent to VA but got confused after reading the thread and as not able to setup MMU so now unclear about issue I am facing.

Just to be clear, do you mean that having set up TCR_EL2 and then enabled the MMU you get the exception?  Or, that you get the exception on programming TCR_EL2 with the MMU still disabled?   I'm assuming the first, but I wanted to check.

Yes, I am doing first, set up TCR_EL2 and then enable MMU. I am getting "Bus error on memory operation" as soon as I write TCR_EL2. My sequence is as follows

1) Set MAIR_EL2 register with attributes (0x000000FF440C0400)

2) Set TCR_EL2 with value (0x80923518) where  T0SZ=24, IRGN0=01, ORGN0=01,SH0=11,TG0=4K granule and PS=40 bits. (I get "Bus error" at this stage)

3) Set TTBR0_EL2 with L0 page table address

4) Set SCTLR_EL2 enabling MMU

Can you give the ESR_EL2 and FAR_EL2 (I'm assuming you're taking the exception to EL2) values

As I get bus error my ESR_EL2 from debugger shows 0x0 and FAR_EL2 is some random address as 0x9FFFFFFF

Initially the most likely answer would be that your tables are mapping an invalid physical address.  As the problem appeared when you increased the size of the VA space, and hence inserted the L0 table, the L0 table would seem like the most likely candidate.  I'm guessing you have the first entry pointed at the original L1 table, is that correct?  What is in the other entry?

I am not sure as I get bus error even before setting TTBR0_EL2 so don't understand if it could be problem due to L0 table ?

Yes first entry for L0 table is = ((L1 page table address & 0xfffffffffffff000) | 0x3 ) similar for other block descriptors.

All other 511 entries of L0 table are zero as still I am having only first 512GB block mapped.

• Physical address of the L0 table  = 0x80208000
• Value of TTBR0_EL2  = (Not getting set as getting bus error as soon as set TCR_EL2)
• Value of TCR_EL2 = 0x80923518
• Value of the entries in the L0 table = { 1st entry is = 80209003, and all other = 0x0 }
• Physical address of the L1 table(s) pointed at by the non-faulting L0 table entries (remember, L0 tables can't contain block descriptors) = physical address for L1 table is 0x80209000. Also If L0 tables can't contain block descriptor than how to set it ? Do I have to set direct L1 physical address ? While looking into "D4-24 Complete stage 1 translation of a 48-bit address using the 4KB translation granule" I do see L0 level descriptor has bits[0:1] set to 0x3.

Also just to confirm if I follow same above sequence and set TCR_EL2 (T0SZ=25) and use L1 stage page tables I don't see any issues. Please let me know what I am missing here ?

Thanks

Hi Martin,

Thanks. I also had understanding that PA range independent to VA but got confused after reading the thread and as not able to setup MMU so now unclear about issue I am facing.

Just to be clear, do you mean that having set up TCR_EL2 and then enabled the MMU you get the exception?  Or, that you get the exception on programming TCR_EL2 with the MMU still disabled?   I'm assuming the first, but I wanted to check.

Yes, I am doing first, set up TCR_EL2 and then enable MMU. I am getting "Bus error on memory operation" as soon as I write TCR_EL2. My sequence is as follows

1) Set MAIR_EL2 register with attributes (0x000000FF440C0400)

2) Set TCR_EL2 with value (0x80923518) where  T0SZ=24, IRGN0=01, ORGN0=01,SH0=11,TG0=4K granule and PS=40 bits. (I get "Bus error" at this stage)

3) Set TTBR0_EL2 with L0 page table address

4) Set SCTLR_EL2 enabling MMU

Can you give the ESR_EL2 and FAR_EL2 (I'm assuming you're taking the exception to EL2) values

As I get bus error my ESR_EL2 from debugger shows 0x0 and FAR_EL2 is some random address as 0x9FFFFFFF

Initially the most likely answer would be that your tables are mapping an invalid physical address.  As the problem appeared when you increased the size of the VA space, and hence inserted the L0 table, the L0 table would seem like the most likely candidate.  I'm guessing you have the first entry pointed at the original L1 table, is that correct?  What is in the other entry?

I am not sure as I get bus error even before setting TTBR0_EL2 so don't understand if it could be problem due to L0 table ?

Yes first entry for L0 table is = ((L1 page table address & 0xfffffffffffff000) | 0x3 ) similar for other block descriptors.

All other 511 entries of L0 table are zero as still I am having only first 512GB block mapped.

• Physical address of the L0 table  = 0x80208000
• Value of TTBR0_EL2  = (Not getting set as getting bus error as soon as set TCR_EL2)
• Value of TCR_EL2 = 0x80923518
• Value of the entries in the L0 table = { 1st entry is = 80209003, and all other = 0x0 }
• Physical address of the L1 table(s) pointed at by the non-faulting L0 table entries (remember, L0 tables can't contain block descriptors) = physical address for L1 table is 0x80209000. Also If L0 tables can't contain block descriptor than how to set it ? Do I have to set direct L1 physical address ? While looking into "D4-24 Complete stage 1 translation of a 48-bit address using the 4KB translation granule" I do see L0 level descriptor has bits[0:1] set to 0x3.

Also just to confirm if I follow same above sequence and set TCR_EL2 (T0SZ=25) and use L1 stage page tables I don't see any issues. Please let me know what I am missing here ?

Thanks

Hi,

2) Set TCR_EL2 with value (0x80923518) where  T0SZ=24, IRGN0=01, ORGN0=01,SH0=11,TG0=4K granule and PS=40 bits. (I get "Bus error" at this stage)

This is almost certainly caused by the MMU already being on at the point that you write to TCR_EL2, which in your case is resulting in a virtual address being translated to an invalid physical address because TTBR0_EL2 hasn't been set to the correct value yet. At the entry point to your program, please can you do this to ensure that the MMU is turned off:

LDR X0, =0x30C50830

MSR SCTLR_EL2, X0

This will safely disable the MMU and caches at EL2 while reserving SCTLR_EL2's RES1 bits.

Yes first entry for L0 table is = ((L1 page table address & 0xfffffffffffff000) | 0x3 ) similar for other block descriptors.

This is not the correct way to generate a table descriptor. From the ARMv8-A Architecture Reference Manual (DDI 0487A.f) section D4.4.1, the table descriptor at 4KB granularity expects bits [47:m] to be bits [47:m] of the next-level table's physical address. Bits [63:48] of the table descriptor include RES0 bits, some ignored bits, and some table attribute bits such as NSTable, APTable, XNTable, and PXNTable. The code you are using to generate your table descriptor is setting all of these bits to 1, including the RES0 bits [51:48].

Ash.

Hi Ash,

I am getting another issue when I setup my stage 2 page tables. I am again configuring for 40bit address range with VTCR_EL2 (T0SZ=24, TG0=00, SL0 = 2(starting at L0), PS=40bits ).

I am again getting "Bus error on memory operation" when I try to got to Guest VM memory even though my stage 2 translation tables are correct (I am mapping EL1 space pages and setting up stage 2 translations) which I verified using DS-5.

I also made sure that EL1 stage 1 translation is disabled and MMU is disabled by setting (SCTLR_EL1 = 0x30D00800).

I am getting issue when I tried to do "eret" to EL1 from EL2 mode. Please let me know what I am doing wrong ?

Thanks.