Hi,
I was trying to change my MMU setup from 39bit address space to 40bit address space in Juno.
Previously I was successfully able to map 39bit address space by setting T0SZ=25 and using L1 level page tables.
Now I am trying to enable MMU configuring L0 level page tables but as soon as I write TCR_EL2 and T0SZ=24 I am getting "Bus error on memory operation".
I faced this issue before when I was setting wrong T0SZ value but now I am setting T0SZ=24 which should be the value for 40bit virtual space.
Is it possible in Juno to have MMU with 40bit address space > 512GB ? I read another link (Re: Re: ARMv8 mmu problem)
but it is confusing if it is possible or not as ID_AA64MMFR0_EL1 register show Juno supports 40bit and memory map states upper 512GB reserved based on above link.
I would like to know how to identify then the value of T0SZ as apart from ID register and page table granularity it seems platform memory map has to be considered ?
Another issue is I am mapping my VA -> IPA -> PA all to 39bit address space and not sure if Linux has any restriction that PA/IPA needs to be wider than VA ?
Thanks.
Hi Ash,
I am getting another issue when I setup my stage 2 page tables. I am again configuring for 40bit address range with VTCR_EL2 (T0SZ=24, TG0=00, SL0 = 2(starting at L0), PS=40bits ).
I am again getting "Bus error on memory operation" when I try to got to Guest VM memory even though my stage 2 translation tables are correct (I am mapping EL1 space pages and setting up stage 2 translations) which I verified using DS-5.
I also made sure that EL1 stage 1 translation is disabled and MMU is disabled by setting (SCTLR_EL1 = 0x30D00800).
I am getting issue when I tried to do "eret" to EL1 from EL2 mode. Please let me know what I am doing wrong ?
For anyone with similar issues, Martin has answered this in a separate thread.