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The bottom bit in the address of a BX instruction is used to encode the "eXchange" - the state change from ARM to Thumb. So the address you feed the BX instruction looks fine.I would check the following:Does the destination address exist (i.e. is it mapped in the MMU)?[list]YesDoes the destination address contain code (i.e. is it mapped as executable in the MMU)?YesDoes the destination address contain an instruction which is valid encoding for the current instruction set?YesIf you are using ARM and Thumb code make sure it is all compiled for "interworking"YesCheck the Fault Status Register in CP15 - this will give more info about why an abort was raised.Status is 0x7; TTBR0 - 0xB7568B58, CR - 0x00457B7DStatus 0x7 translates to b0111 - Translation Fault. How the cpu can crash during translation?[/list]What platform are you running on, and which core revision?Cheers, Iso
It is a translation fault for the page walk, which implies that you are branching to an invalid address (the L2 page table entry is a fault page). If you expect this address to be valid check your page table creation code.See http://infocenter.ar...h/Babicjaf.html
Any Update? The issue solved? What is the root cause?
Did you e-mail, or were you hoping they'd look at the thread?