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Prefetch Abort due to unaligned PC.
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Prefetch Abort due to unaligned PC.
Nikhil Girdhar
over 12 years ago
Note: This was originally posted on 22nd August 2011 at
http://forums.arm.com
Hi,
I am working on ARM1136 processor in Thumb mode.
Problem
I am getting a prefetch abort while executing an instruction. Program Counter at this instant is odd.
Description
My source code has few instructions as below...
....
[color=#FF0000] [/color]bx lr [color=#FF0000] [/color];lr = 0xB76B2A39 i.e. some odd value
After executing this instruction the code jumps to the location 0xB76B2A38 (pc = lr & 0xFFFFFFFE) which has the instruction as below
Address 0xB76B2A38: [color=#FF0000] [/color]ldr r0, #0xB76B5DAC [color=#FF0000] [/color];prefetch abort.
The above instruction generates a prefetch abort as the pc value is odd 0xB76B2A39.
BX Instruction description
BX Rm instruction ensures that the location that you jump to is half a word aligned. i.e. pc = lr & 0xFFFFFFE
ARM thumb mode requires that pc should always be half a word aligned.
In this case pc alignment (to be done by the processor) did not take place.
How can I figure out whether the processor is goofing up or there is some software issue?
Thank you.
Nikhil.
Parents
Peter Harris
over 12 years ago
Note: This was originally posted on 22nd August 2011 at
http://forums.arm.com
The bottom bit in the address of a BX instruction is used to encode the "eXchange" - the state change from ARM to Thumb. So the address you feed the BX instruction looks fine.
I would check the following:
Does the destination address exist (i.e. is it mapped in the MMU)?
Does the destination address contain code (i.e. is it mapped as executable in the MMU)?
Does the destination address contain an instruction which is valid encoding for the current instruction set?
If you are using ARM and Thumb code make sure it is all compiled for "interworking"
Check the Fault Status Register in CP15 - this will give more info about why an abort was raised.
What platform are you running on, and which core revision?
Cheers,
Iso
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Peter Harris
over 12 years ago
Note: This was originally posted on 22nd August 2011 at
http://forums.arm.com
The bottom bit in the address of a BX instruction is used to encode the "eXchange" - the state change from ARM to Thumb. So the address you feed the BX instruction looks fine.
I would check the following:
Does the destination address exist (i.e. is it mapped in the MMU)?
Does the destination address contain code (i.e. is it mapped as executable in the MMU)?
Does the destination address contain an instruction which is valid encoding for the current instruction set?
If you are using ARM and Thumb code make sure it is all compiled for "interworking"
Check the Fault Status Register in CP15 - this will give more info about why an abort was raised.
What platform are you running on, and which core revision?
Cheers,
Iso
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