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Cortex-A9 Cause for wake up from low power mode ( WFI )

Virupax ss
Note: This was originally posted on 26th July 2011 at http://forums.arm.com

Hi
I am using cortex-A9 powered soc, it has two a9 cores.

when cpu1 is put in low power mode using the wfi, the processor wakes up unintentionally.
From the Cortex-A9 MPCore TRM, the causes for the wake ups are

The transition from the WFI Standby mode to the Run modeis caused by:

"¢ An interrupt, masked or unmasked.

"¢ An asynchronous data abort, regardless of the value ofthe CPSR.A bit. A pending wake-up event prevents the processor from enteringlow power mode.

"¢ A debug request, regardless of whether debug isenabled.

"¢ A cp15 maintenance request from another processor

"¢ A reset.

Since all Irq's are routed to cpu0, irq is not a cause for the spurious wakeup,
The only cause seems to be the "cp15 maintenance request from another processor"

How to check which of the CP15 maintenance request caused the wakup
is it possible to disable the cp15 maintenance requests from other cpu before going to low power mode.


Thanks
  • Note: This was originally posted on 27th September 2011 at http://forums.arm.com

    Thanks for the reply.
    In WFI mode , does the CPU need to handle the maintenance requests ? Does the FW bit can be set to 0 in WFI mode ?
  • Note: This was originally posted on 10th October 2011 at http://forums.arm.com


    Hi
    I am using cortex-A9 powered soc, it has two a9 cores.

    when cpu1 is put in low power mode using the wfi, the processor wakes up unintentionally.
    From the Cortex-A9 MPCore TRM, the causes for the wake ups are

    The transition from the WFI Standby mode to the Run modeis caused by:

    "¢ An interrupt, masked or unmasked.

    "¢ An asynchronous data abort, regardless of the value ofthe CPSR.A bit. A pending wake-up event prevents the processor from enteringlow power mode.

    "¢ A debug request, regardless of whether debug isenabled.

    "¢ A cp15 maintenance request from another processor

    "¢ A reset.

    Since all Irq's are routed to cpu0, irq is not a cause for the spurious wakeup,
    The only cause seems to be the "cp15 maintenance request from another processor"

    How to check which of the CP15 maintenance request caused the wakup
    is it possible to disable the cp15 maintenance requests from other cpu before going to low power mode.


    Thanks




    I hope you are considering WFE as well. For WFE, a number of specified events exist, including another processor in an MP system executing the SEV instruction. A request from SCU can also wake up the clock for a cache coherency operation in an MP system.
  • Note: This was originally posted on 10th October 2011 at http://forums.arm.com


    I hope you are considering WFE as well. For WFE, a number of specified events exist, including another processor in an MP system executing the SEV instruction. A request from SCU can also wake up the clock for a cache coherency operation in an MP system.


    And extra care for the recommended DSB memory barrier before WFI or WFE to ensure the pending memory transactions complete.
  • Arm Employee Badge
    Note: This was originally posted on 26th July 2011 at http://forums.arm.com

    I think it means cache/tlb/btac broadcast operations.  If so, these are enabled/disable by the FW bit in the CP15 Aux Control Register.  However, I'm not sure you really want to disable this!  Cache maintenance broadcasting is part of the coherency management support provided by the A9 MPCore.  If you want a coherent system you in almost certainly want this feature enabled.

    The thing to remember with WFI and WFE is that they aren't there for synchronization.  They are are there for power saving.  So on waking from stand-0by your code should always check to see why it woke up.  Or to put it another way, whether it should go back to sleep.