• Locked Locked
  • Replies 4 replies
  • Subscribers 119 subscribers
  • Views 4866 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-A9 Cause for wake up from low power mode ( WFI )

Virupax ss
Note: This was originally posted on 26th July 2011 at http://forums.arm.com

Hi
I am using cortex-A9 powered soc, it has two a9 cores.

when cpu1 is put in low power mode using the wfi, the processor wakes up unintentionally.
From the Cortex-A9 MPCore TRM, the causes for the wake ups are

The transition from the WFI Standby mode to the Run modeis caused by:

"¢ An interrupt, masked or unmasked.

"¢ An asynchronous data abort, regardless of the value ofthe CPSR.A bit. A pending wake-up event prevents the processor from enteringlow power mode.

"¢ A debug request, regardless of whether debug isenabled.

"¢ A cp15 maintenance request from another processor

"¢ A reset.

Since all Irq's are routed to cpu0, irq is not a cause for the spurious wakeup,
The only cause seems to be the "cp15 maintenance request from another processor"

How to check which of the CP15 maintenance request caused the wakup
is it possible to disable the cp15 maintenance requests from other cpu before going to low power mode.


Thanks
Parents
  • Note: This was originally posted on 10th October 2011 at http://forums.arm.com


    I hope you are considering WFE as well. For WFE, a number of specified events exist, including another processor in an MP system executing the SEV instruction. A request from SCU can also wake up the clock for a cache coherency operation in an MP system.


    And extra care for the recommended DSB memory barrier before WFI or WFE to ensure the pending memory transactions complete.
Reply
  • Note: This was originally posted on 10th October 2011 at http://forums.arm.com


    I hope you are considering WFE as well. For WFE, a number of specified events exist, including another processor in an MP system executing the SEV instruction. A request from SCU can also wake up the clock for a cache coherency operation in an MP system.


    And extra care for the recommended DSB memory barrier before WFI or WFE to ensure the pending memory transactions complete.
Children
No data