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DS5 debug on nvidia TX1 board

vdupre

Hello

I have some problem to connect DS5 (v5.26.2) debugger to nvidia TX1 board. First, I used the "platform configuration" wizard in eclipse for creating TX1 which seems ok except few warnings about devices that does not have any connections (CSTFunnel / CSETM). Then, I created debug configuration (baremetal debug with connect only option). When I try to debug, I have a
"connection Failed" popup with the following message: "Unable to connect to... Reason: Unable to connect to USB:XXXXXX Unable to connect to device APB_0 No connection to target.".

Does somebody successfully connect DS5 debugger to RX1? Any tips would be greatly appreciate!

Thanks in advance!

Vincent

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  • 0 Arm Employee Badge in reply to vdupre
    Hi,
    It is interesting that dbghwconfig got you a configuration whereas PCE didn't. But please bear in mind that dbghwconfig is no longer shipped with DS-5.
    It would be interesting to see/know why PCE was unable to create a config that seemingly didn't work, it should have done, but I don't have access to a board to test this myself I am afraid. If you have any logs then they would be much appreciated.

    Thanks,
    Stuart
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  • 0 Arm Employee Badge in reply to vdupre
    Hi,
    It is interesting that dbghwconfig got you a configuration whereas PCE didn't. But please bear in mind that dbghwconfig is no longer shipped with DS-5.
    It would be interesting to see/know why PCE was unable to create a config that seemingly didn't work, it should have done, but I don't have access to a board to test this myself I am afraid. If you have any logs then they would be much appreciated.

    Thanks,
    Stuart
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  • 0 in reply to Stuart Hirons
    Thanks for the comment! Currently, debugging is ok on the booting core but for the secondary cores, DS5 can't connect to TX1 board and throw "Unable to connect to device ... unknown error" (when debugging with H/W configured with dbghw tool)...
    I will check for the logs and post it this week when using platform configuration tool in eclipse.

    Vincent
  • +1 Arm Employee Badge in reply to vdupre

    Hi Vincent,

    My guess is that the other cores are powered down, but that the board has some proprietary reset/power controller that DS-5 is not aware of.

    Consequently, the tool is trying to to connect to the cores that are powered down, expecting at least some of the debug logic to be powered up but finding that in fact the whole core is powered down, including the debug power domain on that core.

    Assuming you have access to a TRM/Programmers Reference Guide for the SoC, have a look at the sections relating to reset and/or power and see if there are any specific registers that need to be written in order to power up the core.

    This assumes that you are developing bare-metal. If you have Linux running then of course Linux is performing the power management and can be quite aggressive in order to keep power consumption down (this can include such policies as disabling clocks and/or power to cores that are not running/used, disabling debug clock and so forth).

    The Linux kernel code might have the answer, if you don't have a TRM for the SoC.


    I hope that helps ?

    Regards,
    Stuart

  • 0 in reply to Stuart Hirons

    Hello Stuart,

    You were right, the secondary cores weren't power on. I thought that u-boot did the power-up but it wasn't the case! Also, secondary cores booting on TX1 is done via PSCI interface, way easier than the power-up routine described in TX1 board TRM!

    Thanks again for the help

    Vincent