DS5 debug on nvidia TX1 board

Hi Vincent,

My guess is that the other cores are powered down, but that the board has some proprietary reset/power controller that DS-5 is not aware of.

Consequently, the tool is trying to to connect to the cores that are powered down, expecting at least some of the debug logic to be powered up but finding that in fact the whole core is powered down, including the debug power domain on that core.

Assuming you have access to a TRM/Programmers Reference Guide for the SoC, have a look at the sections relating to reset and/or power and see if there are any specific registers that need to be written in order to power up the core.

This assumes that you are developing bare-metal. If you have Linux running then of course Linux is performing the power management and can be quite aggressive in order to keep power consumption down (this can include such policies as disabling clocks and/or power to cores that are not running/used, disabling debug clock and so forth).

The Linux kernel code might have the answer, if you don't have a TRM for the SoC.

I hope that helps ?

Regards,
Stuart

Hi Vincent,

My guess is that the other cores are powered down, but that the board has some proprietary reset/power controller that DS-5 is not aware of.

Consequently, the tool is trying to to connect to the cores that are powered down, expecting at least some of the debug logic to be powered up but finding that in fact the whole core is powered down, including the debug power domain on that core.

Assuming you have access to a TRM/Programmers Reference Guide for the SoC, have a look at the sections relating to reset and/or power and see if there are any specific registers that need to be written in order to power up the core.

This assumes that you are developing bare-metal. If you have Linux running then of course Linux is performing the power management and can be quite aggressive in order to keep power consumption down (this can include such policies as disabling clocks and/or power to cores that are not running/used, disabling debug clock and so forth).

The Linux kernel code might have the answer, if you don't have a TRM for the SoC.

I hope that helps ?

Regards,
Stuart

Hello Stuart,

You were right, the secondary cores weren't power on. I thought that u-boot did the power-up but it wasn't the case! Also, secondary cores booting on TX1 is done via PSCI interface, way easier than the power-up routine described in TX1 board TRM!

Thanks again for the help

Vincent