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Cortex M3 Cache disable

Note: This was originally posted on 23rd August 2010 at http://forums.arm.com

Hi everybody,

I have here an STM32F103ZE with an Cortex M3 core and I need to disable the cache. But unfortunatly I dont find any information about it. If I understood it right, I have to use the MPU - registers to disable the cache but i dont know which.
Hope you can help me!

Kind regards
Mathias

Mathias Dubdidu over 12 years ago

Note: This was originally posted on 24th August 2010 at http://forums.arm.com

Hi all,

well i will try to explain, what i want to do:
I have an data array with 12 bit. These bits i want to give out on a pin. To get an exact timing (about 500ns) between the bits i tryed to make a while loop with a timer. But with this i have lots of jitters. So i thought i can switch of the cache to avoid them.
But well now i have to try something else. Is there any assembler reference for the Cortex M3? I havent found one yet.

Kind regards
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Joseph Yiu over 12 years ago

Note: This was originally posted on 25th August 2010 at http://forums.arm.com

In addition:

1. Use interrupts instead of polling loops

2. Most STM32 parts has a flash memory prefetcher. It can affect the jitter by a small amount.
This can be turned off by writing to the Flash access control register (FLASH_ACR).
[url="http://www.st.com/stonline/products/literature/pm/17100.pdf"]http://www.st.com/stonline/products/literature/pm/17100.pdf[/url]
(I don't know if this document applies to the part you are using).

You can ask STM32 specific questions on STM32 forum on
[url="https://my.st.com/public/STe2ecommunities/mcu/Lists/ARM%20CortexM3%20STM32/AllItems.aspx"]https://my.st.com/public/STe2ecommunities/m...2/AllItems.aspx[/url]
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David Clark over 12 years ago

Note: This was originally posted on 23rd August 2010 at http://forums.arm.com

Hi everybody,

I have here an STM32F103ZE with an Cortex M3 core and I need to disable the cache. But unfortunatly I dont find any information about it. If I understood it right, I have to use the MPU - registers to disable the cache but i dont know which.
Hope you can help me!

Kind regards
Mathias

HUH??? The CM3 has no cache. Maybe there is some on-chip (but off-core) high-speed RAM you're talking about?

Could you please give more details (be specific!) so we can try to help - thanks.
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Peter Harris over 12 years ago

Note: This was originally posted on 23rd August 2010 at http://forums.arm.com

There is no cache in the Cortex-M3 core itself, although a particular ASIC may include one outside of the device through a memory-mapped interface. It is typical for the core to be directly connected to an on-device SRAM.

What are you actually trying to achieve?
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Peter Harris over 12 years ago

Note: This was originally posted on 24th August 2010 at http://forums.arm.com

>> So i thought i can switch off the cache to avoid them.

There is no cache in the Cortex-M3 ...

>> To get an exact timing (about 500ns) between the bits i tryed to

Assuming you are clocking the ST device it at its maxmum frequency (72MHz) then 500 ns is only 13.8 cycles. Not all instructions are a single cycle (a branch takes 3 cycles), and your total loop overhead between timer tests is going to be more than just the branch. Assuming 8 cycles of loop and timer test overhead between timer tests then you are going to get up to 350 ns of overshoot on your 500ns timing window.

So my conculsion would be your timing loop design doesn't work for this type of task. You could try writing a bit and then having a sequence of 14 "NOP" instructions which are known to take a single cycle and then the next bit (i.e. no branches, timers, loops, or at least a simple calibrated loop which you know takes 14 cycles).

>> Is there any assembler reference for the Cortex M3? I havent found one yet.

You can sign up for the ARM-V7M architecture manual (requires a user account) from here:

[url="https://silver.arm.com/download/eula.tm?pv=1073296"]https://silver.arm.com/download/eula.tm?pv=1073296[/url]

For assembler syntax check out the manual for your tools (GCC, RVCT, DS-5, etc).

Iso
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