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Cortex M3 Cache disable

Mathias Dubdidu
Note: This was originally posted on 23rd August 2010 at http://forums.arm.com

Hi everybody,

I have here an STM32F103ZE with an Cortex M3 core and I need to disable the cache. But unfortunatly I dont find any information about it. If I understood it right, I have to use the MPU - registers to disable the cache but i dont know which.
Hope you can help me!

Kind regards
Mathias
Parents
  • Arm Employee Badge
    Note: This was originally posted on 24th August 2010 at http://forums.arm.com

    >> So i thought i can switch off the cache to avoid them.

    There is no cache in the Cortex-M3 ...

    >> To get an exact timing (about 500ns) between the bits i tryed to

    Assuming you are clocking the ST device it at its maxmum frequency (72MHz) then 500 ns is only 13.8 cycles. Not all instructions are a single cycle (a branch takes 3 cycles), and your total loop overhead between timer tests is going to be more than just the branch. Assuming 8 cycles of loop and timer test overhead between timer tests then you are going to get up to 350 ns of overshoot on your 500ns timing window.

    So my conculsion would be your timing loop design doesn't work for this type of task. You could try writing a bit and then having a sequence of  14 "NOP" instructions which are known to take a single cycle and then the next bit (i.e. no branches, timers, loops, or at least a simple calibrated loop which you know takes 14 cycles).

    >> Is there any assembler reference for the Cortex M3? I havent found one yet.

    You can sign up for the ARM-V7M architecture manual (requires a user account) from here:

    [url="https://silver.arm.com/download/eula.tm?pv=1073296"]https://silver.arm.com/download/eula.tm?pv=1073296[/url]

    For assembler syntax check out the manual for your tools (GCC, RVCT, DS-5, etc).

    Iso
Reply
  • Arm Employee Badge
    Note: This was originally posted on 24th August 2010 at http://forums.arm.com

    >> So i thought i can switch off the cache to avoid them.

    There is no cache in the Cortex-M3 ...

    >> To get an exact timing (about 500ns) between the bits i tryed to

    Assuming you are clocking the ST device it at its maxmum frequency (72MHz) then 500 ns is only 13.8 cycles. Not all instructions are a single cycle (a branch takes 3 cycles), and your total loop overhead between timer tests is going to be more than just the branch. Assuming 8 cycles of loop and timer test overhead between timer tests then you are going to get up to 350 ns of overshoot on your 500ns timing window.

    So my conculsion would be your timing loop design doesn't work for this type of task. You could try writing a bit and then having a sequence of  14 "NOP" instructions which are known to take a single cycle and then the next bit (i.e. no branches, timers, loops, or at least a simple calibrated loop which you know takes 14 cycles).

    >> Is there any assembler reference for the Cortex M3? I havent found one yet.

    You can sign up for the ARM-V7M architecture manual (requires a user account) from here:

    [url="https://silver.arm.com/download/eula.tm?pv=1073296"]https://silver.arm.com/download/eula.tm?pv=1073296[/url]

    For assembler syntax check out the manual for your tools (GCC, RVCT, DS-5, etc).

    Iso
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