NEW on Cortex-M3 STM32F103B IAR

Hi there, some of your qustions are not exactly clear. Hope my answers/suggestions would help.

1- how can I show the importance of latency and jitter in C coding (systick with GPIO?!)  (refering to this document: rtos-comparison-EN.pdf ).
The minimum latency and jitter depends on the waitstate of the system as well as interrupt latency of the processor. For best testing result you should try to run the system with a clock configuration with minimum wait state. I think for STM32 it is 24MHz for zero wait state on flash.  The Cortex-M3 can give you 12 cycle interrupt latency for zero wait state.  But access to peripherals via bus bridge might result in waitstate and hence increase the interrupt latency slight.

The idea of measuring interrupt latency using GPIO is possible, but don't forget that your access to the GPIO inside the interrupt handler will result in extra clock cycles.  For a fair comparison you should try to carry out a measurement of I/O access time.  The I/O access latency is dependent on the microcontroller product design, C compiler, and clocksstem settings in the microcontroller.

The importance of latency and jitter depends on your applications.  For simple applications a bit of interrupt latency and jitter does not matter.  But in some non-linear control applications a large jitter can result in failure in the control algorithm.  That is why Cortex-M3 is good for control applications: Exclusing the cases where interrupt is blocked by a higher priority interrupts or interrupt masking register, the interrupt latency is 12 cycles plus extra cycles results from wait states, which is usually a very small number.  Cortex-M0 even have a zero jitter feature - not sure if NXP LPC111x include this feature.
Most other archtectures usually have non-deterministic interrupt latency.



2- hwo can show me, a code in C that details a cotext switch.

Context switching is unlikely to be implemented in C.  In context switching you would want to have total control on individual register read/write. This need to be done in assembly.
There are a number of open source OS available for Cortex-M3, please look at their code to try to understand the implementation.

3- DMA multilayering communication between interfaces and memories is the default configuration in cortex-M3; how can i show the importance of this feature, in benchmarking.

The Cortex-M3 itself does not have DMA feature.  The DMA feature is added by individual microcontroller vendor in their design. There are various performance points you can focus on, depending on your applications, for example:
- maximum bandwidth of the DMA operation,
- maximum performance penalty of the procesor while DMA is running at a fixed rate in the background,
- impact to interrupt latency jitter when DMA is running at a fixed rate in the back ground,
- improvement of application peformance by using DMA,
- comparison of DMA features between different Cortex-M3 microcontrollers, etc.

Depending the target of your benchmark report, you might want to look at one or more of these areas.
Is it an academic research paper you are preparing?

Hi Slim,

Thanks for the update.

The measurement you have done is interesting.

There are a few things you might need to look at:
- Are the two tests carried out in the same setup?
  (same clock frequency, same peripheral clock frequency,
  same wait state configuration, same OS tick frequency).
- I guess you measured the duration of the pulse in the GPIO.
  Since both rising and falling edge of the pulse can be affected by jitter, the result might not be accurate.
  Ideally you should use a constant timing source which is synchronous to the processor clock
  and divided to the same test loop frequency to drive the trigger input of the oscilloscope.
  I know that might not be possible with the current setup, but it might worth mention in your paper.
  Using on chip timer measurment is one good way to solve this problem.
- Other jitter source - e.g. Potential jitter from on chip PLL

Regarding measurement of context switching time:
Develop two tasks, one toggle a GPIO pin and the other task toggle another pin.
You can then see the gap between the activities of the two tasks with an oscilloscope.
Of course, there could be some timing inaccuracy because it depends on the length of the toggling loop, the access time of the GPIO registers, and which instruction it stop at most often during context switching.

Unfortunately I don't have any STM32 board so can't develop test code for it.
You can try post your question on this to STM32 forum
[url="https://my.st.com/public/STe2ecommunities/mcu/Lists/ARM%20CortexM3%20STM32/AllItems.aspx"]my.st.com/.../url]
Maybe someone will be able help you there.

regards,
Joseph

thanks a lot Joseph,

yes, I'm preparing an academic research paper intitled "Real-Time Performmance two RTOS running on STM32 (ARM cortex-M3 Archtecture): FreeRTOS and µc/osII"

I'm using the STM32F103B-Eval Board from IAR systems with its IAR workbench IDE.
within i'm trying to do an application containig two configuration:

1- FreeRTOS config: OS_lib+STM32 Lib+ cortexm3 lib+ main(interrept latency with systick+ function using DMA+ other real-time fucntions not fixed yet)

2- µc/osII configuration:  OS_lib+ BSP lib+ STM32 Lib+ cortexm3 lib+ main(interrept latency with systick+ function using DMA+ other real-time fucntions not fixed yet).

Best regards,
Slim