Arm Development Studio forum LDR parallelism on arm926ej-s processors...?

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LDR parallelism on arm926ej-s processors...?

Note: This was originally posted on 2nd November 2009 at http://forums.arm.com

Hi everyone,

(I know it sounds like a trivial question but...)

What does the arm926ej-s do while it is filling a data cache line? That is, can you execute other normal ALU opcodes while a LDR completes (as long as you don''t try to read the LDR's target register from the register file), or does the LDR stall the processor until such time as the write to the register file is complete?

I've gone through countless ARM tech ref guides trying to work out what behaviour to expect here - please feel free to suggest any relevant tech documentation I should be looking at (there wasn't anything in the ARMv5 architecture guide or the ARM System Developer's Guide, etc).

Thanks, ....Nick Pelling....