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LDR parallelism on arm926ej-s processors...?

Nick Pelling
Note: This was originally posted on 2nd November 2009 at http://forums.arm.com

Hi everyone,

(I know it sounds like a trivial question but...)

What does the arm926ej-s do while it is filling a data cache line? That is, can you execute other normal ALU opcodes while a LDR completes (as long as you don''t try to read the LDR's target register from the register file), or does the LDR stall the processor until such time as the write to the register file is complete?

I've gone through countless ARM tech ref guides trying to work out what behaviour to expect here - please feel free to suggest any relevant tech documentation I should be looking at (there wasn't anything in the ARMv5 architecture guide or the ARM System Developer's Guide, etc).

Thanks, ....Nick Pelling....
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  • Arm Employee Badge
    Note: This was originally posted on 2nd November 2009 at http://forums.arm.com

    The 926 pipeline is serial - so a following instruction can not progress until the current instruction does. 

    If the LDR hits in the cache, that shouldn't affect the susequent ADD. 

    If the LDR misses, the ADD will be stalled while the load completes.  That said, the core will fetch the requested word first.  So you only wait for the required data, not the complete cache line.

    The ARM11s have support for out-standing loads.
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  • Arm Employee Badge
    Note: This was originally posted on 2nd November 2009 at http://forums.arm.com

    The 926 pipeline is serial - so a following instruction can not progress until the current instruction does. 

    If the LDR hits in the cache, that shouldn't affect the susequent ADD. 

    If the LDR misses, the ADD will be stalled while the load completes.  That said, the core will fetch the requested word first.  So you only wait for the required data, not the complete cache line.

    The ARM11s have support for out-standing loads.
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