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The script file (rtsm_launcher.py) failed during execution. Corstone SSE-300

Yev Pril

Hello,

I tried to simulate the Blinky project on the MPS3-SSE-300 (Cotrtex-M55 + Helium).

Before simulation I added to global Path:

g:\Program Files\Arm\FVP_Corstone_SSE-300\
g:\Program Files\Arm\FVP_Corstone_SSE-300\models\Win64_VC2019\

I have errors when I tried to launch the debbuger:
For example:

The script file ( rtsm_launcher.py ) failed during execution:
Failed to launch model FVP_Corstone_SSE-300_Ethos-U55. Command:
FVP_Corstone_SSE-300_Ethos-U55 --iris-server --print-port-number -C fvp_mps3.DISABLE_GATING=1 -C cpu0.FPU=1 -C cpu0.MVE=2
exited with error code: -1073740791

I tried a few commands:
-C fvp_mps3.DISABLE_GATING=1 -C cpu0.FPU=1 -C cpu0.MVE=2

-C cpu0.enable_helium_extension=1 -C cpu0.vfp-present=1 -C cpu0.vfp-enable_at_reset=1

-C cpu0.enable_helium_extension=1 -C cpu0.vfp-present=1 -C cpu0.vfp-enable_at_reset=1 -C cpu0.semihosting-enable=1


Can you please help?


Parents
  • 0 Arm Employee Badge in reply to Yev Pril

    ＞Cannot find device cpu0.cpu0.l1dcache

    I suspect "cpu0.cpu0.l1dcache" is specified somewhere, which is not correct, e.g. cpu0.cpu0 should be cpu0 and l1dcache parameter doesn't seem to exist in the model (see below).

    $ FVP_Corstone_SSE-300_Ethos-U55 --list-params | grep cache
cpu0.DCACHESZ=15                                      # (int   , init-time) default = '0xf'    : Whether the D-cache is included and, if included, the size of it. Bit 0: 0=No D-cache included, 1=D-cache included. Bits [4:1]: 0x0=4KB D-cache, 0x1=8KB D-cache, 0x3=16KB D-cache, 0x7=32KB D-cache, 0xF=64KB D-cache
cpu0.ICACHESZ=15                                      # (int   , init-time) default = '0xf'    : Whether the I-cache is included and, if included, the size of it. Bit 0: 0=No I-cache included, 1=I-cache included. Bits [4:1]: 0x0=4KB I-cache, 0x1=8KB I-cache, 0x3=16KB I-cache, 0x7=32KB I-cache, 0xF=64KB I-cache
cpu0.dcache-state_modelled=0                          # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation
cpu0.dcache-ways=4                                    # (int   , init-time) default = '0x4'    : L1 D-cache ways (sets are implicit from size)
cpu0.icache-state_modelled=0                          # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation
cpu0.icache-ways=2                                    # (int   , init-time) default = '0x2'    : L1 I-cache ways (sets are implicit from size)
mps3_board.smsc_91c111.cache_size=65536               # (int   , init-time) default = '0x10000' : Size of cache memory in SMSC MMU

Reply
  • 0 Arm Employee Badge in reply to Yev Pril

    ＞Cannot find device cpu0.cpu0.l1dcache

    I suspect "cpu0.cpu0.l1dcache" is specified somewhere, which is not correct, e.g. cpu0.cpu0 should be cpu0 and l1dcache parameter doesn't seem to exist in the model (see below).

    $ FVP_Corstone_SSE-300_Ethos-U55 --list-params | grep cache
cpu0.DCACHESZ=15                                      # (int   , init-time) default = '0xf'    : Whether the D-cache is included and, if included, the size of it. Bit 0: 0=No D-cache included, 1=D-cache included. Bits [4:1]: 0x0=4KB D-cache, 0x1=8KB D-cache, 0x3=16KB D-cache, 0x7=32KB D-cache, 0xF=64KB D-cache
cpu0.ICACHESZ=15                                      # (int   , init-time) default = '0xf'    : Whether the I-cache is included and, if included, the size of it. Bit 0: 0=No I-cache included, 1=I-cache included. Bits [4:1]: 0x0=4KB I-cache, 0x1=8KB I-cache, 0x3=16KB I-cache, 0x7=32KB I-cache, 0xF=64KB I-cache
cpu0.dcache-state_modelled=0                          # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation
cpu0.dcache-ways=4                                    # (int   , init-time) default = '0x4'    : L1 D-cache ways (sets are implicit from size)
cpu0.icache-state_modelled=0                          # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation
cpu0.icache-ways=2                                    # (int   , init-time) default = '0x2'    : L1 I-cache ways (sets are implicit from size)
mps3_board.smsc_91c111.cache_size=65536               # (int   , init-time) default = '0x10000' : Size of cache memory in SMSC MMU

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