The script file (rtsm_launcher.py) failed during execution. Corstone SSE-300

Thanks for your reply!

I changed to mps3_board. and the issue with rtsm_launcher.py are gone.

But, I have another issue "Cannot find device cpu0.cpu0.l1dcache".


I tried 
-C mps3_board.DISABLE_GATING=1 -C cpu0.FPU=1 -C cpu0.MVE=2
or 
-C cpu0.semihosting-enable=1 -C cpu0.FPU=1 -C cpu0.MVE=2

Can you help please?



+ Additional question:
I need to figure out the cycle consumption. I have found this thread:

https://community.arm.com/support-forums/f/soc-design-and-simulation-forum/51314/run-problem-on-the-corstone-sse-300-mps3-simulator/173765#173765

As far as I understand, we need to work with the register for M55: CM_DWT_CONTROL. 
Or have there been any changes during this time?

Thanks.

Thanks for your reply!

I changed to mps3_board. and the issue with rtsm_launcher.py are gone.

But, I have another issue "Cannot find device cpu0.cpu0.l1dcache".


I tried 
-C mps3_board.DISABLE_GATING=1 -C cpu0.FPU=1 -C cpu0.MVE=2
or 
-C cpu0.semihosting-enable=1 -C cpu0.FPU=1 -C cpu0.MVE=2

Can you help please?



+ Additional question:
I need to figure out the cycle consumption. I have found this thread:

https://community.arm.com/support-forums/f/soc-design-and-simulation-forum/51314/run-problem-on-the-corstone-sse-300-mps3-simulator/173765#173765

As far as I understand, we need to work with the register for M55: CM_DWT_CONTROL. 
Or have there been any changes during this time?

Thanks.

The connection error suggests that you are not connecting to the correct model.

I am not aware of any changes regarding DWT_CONTROL.

＞Cannot find device cpu0.cpu0.l1dcache

I suspect "cpu0.cpu0.l1dcache" is specified somewhere, which is not correct, e.g. cpu0.cpu0 should be cpu0 and l1dcache parameter doesn't seem to exist in the model (see below).

$ FVP_Corstone_SSE-300_Ethos-U55 --list-params | grep cache
cpu0.DCACHESZ=15                                      # (int   , init-time) default = '0xf'    : Whether the D-cache is included and, if included, the size of it. Bit 0: 0=No D-cache included, 1=D-cache included. Bits [4:1]: 0x0=4KB D-cache, 0x1=8KB D-cache, 0x3=16KB D-cache, 0x7=32KB D-cache, 0xF=64KB D-cache
cpu0.ICACHESZ=15                                      # (int   , init-time) default = '0xf'    : Whether the I-cache is included and, if included, the size of it. Bit 0: 0=No I-cache included, 1=I-cache included. Bits [4:1]: 0x0=4KB I-cache, 0x1=8KB I-cache, 0x3=16KB I-cache, 0x7=32KB I-cache, 0xF=64KB I-cache
cpu0.dcache-state_modelled=0                          # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation
cpu0.dcache-ways=4                                    # (int   , init-time) default = '0x4'    : L1 D-cache ways (sets are implicit from size)
cpu0.icache-state_modelled=0                          # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation
cpu0.icache-ways=2                                    # (int   , init-time) default = '0x2'    : L1 I-cache ways (sets are implicit from size)
mps3_board.smsc_91c111.cache_size=65536               # (int   , init-time) default = '0x10000' : Size of cache memory in SMSC MMU

I made project for the M55: SSE-300-MPS3 device and tried the Arm SubSystem FVP -> Corstone SSE-300 (MPS3) -> Bare Metal Debug -> Cortex-M55 model.

Could you please tell me which model is correct for this device?

Thanks

I believe it is the Corstone-300 FVP from here:

https://developer.arm.com/downloads/-/arm-ecosystem-fvps

Hm...
I installed the same package and wrote a global path to it.

What model settings would you recommend for the example "Blinky"? Because I have the same error with the example project.

Thanks