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CoreSight base addr and DAP port number

china liu
Note: This was originally posted on 28th March 2013 at http://forums.arm.com

hi, experts:
I am using a JTAG debugger.
It needs to set every cpu core's coresight base in the config page.
So, i have 2 questions:
1. no registers to record every cpu core's coresight base addr?
2. I also need to set DAP port number : 0/1
    So, why need to set DAP port number?
    I think it should be only 1 DAP port in ARM SOC.

best wishes,
  • Note: This was originally posted on 1st April 2013 at http://forums.arm.com

    hi, maheshp:
    Thanks for your response!
    Take a dual core ARM Soc as an example.
    Every core has its own CoreSight base address.
    And i have to set every core's CoreSight base address in an JTAG debugger.
    So, my question is:
    Is there a dedicated register for saving every CPU core's corresponding CoreSight base address?

    best wishes,
  • Note: This was originally posted on 2nd April 2013 at http://forums.arm.com

    hi，Sandeep:
    Thanks for your reply!
    It seems every CPU core's CoreSight base addr is equal to the CoreSight's ROM table address?



    best wishes,
  • Note: This was originally posted on 1st April 2013 at http://forums.arm.com

    Typically a debug component's base address will be stored in table called the ROM table. To discover debug components present in the system/SOC, an external debugger must do a topology detection by reading the contents of the ROM table that will give the base addresses of various debug components and then reading the Component ID and Periph ID registers (which must be at fixed offset from the component base address as per Coresight Architecture) specific to the debug component being discovered to identify it's details and type (e.g: an ARM Cortex-A7 processor will have some unique values in its Component & Periph ID registers). The system base address of this ROM table must be known to the debugger beforehand and can be unique for every SOC design. However ARM has some recommendation for the base address of this ROM table. There could be multiple levels of ROM tables present in a SOC/system.

    Hope this helps.

    hi, maheshp:
    Thanks for your response!
    Take a dual core ARM Soc as an example.
    Every core has its own CoreSight base address.
    And i have to set every core's CoreSight base address in an JTAG debugger.
    So, my question is:
    Is there a dedicated register for saving every CPU core's corresponding CoreSight base address?

    best wishes,
  • Note: This was originally posted on 1st April 2013 at http://forums.arm.com

    Hi,
      Can you state your query in more detail?

    Regards