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data & unified cache

baskaran chidambaram
Note: This was originally posted on 9th March 2013 at http://forums.arm.com

In the A8 cache registers i see that the data cache tied to Unified cache - for enabling, cleaning etc. Any reason for this?

Regards
Baskaran
  • Note: This was originally posted on 10th March 2013 at http://forums.arm.com

    In the documents, the Data and unified cache are affected by single configuration. For eg
    "c6 2 Invalidate Data or Unified cache line by Set/Way"
    from http://infocenter.ar...k/Babhejba.html

    why there no separate configuration for Unified cache. why it has to be clubbed with Data cache?
  • Arm Employee Badge
    Note: This was originally posted on 10th March 2013 at http://forums.arm.com

    What do you mean by "tied to"? You can do cache maintenance on the L1 without explicitly impacting the L2 (there will be impacting side effects from any line evictions from the L1 of course).
  • Arm Employee Badge
    Note: This was originally posted on 11th March 2013 at http://forums.arm.com

    [color=#222222][font=arial, helvetica, sans-serif][size=2]> why there no separate configuration for Unified cache. why it has to be clubbed with Data cache? [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]At a given level in the cache hierarchy you will either have a separate I and D cache, or a unified cache. You never have both a D cache and a unified cache at the same level. [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]For 99% of ARM implementations you will have separate I and D at level 1, and a unified level 2. The usage of the set way logic selects which cache level you want to invalidate, so you can target either the D or the U cache depending on what level you have selected.[/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]You group the I cache by itself because it is fundamentally different to the other two - D and U can both contain modified data, the I cache cannot, so many encodings make no sense for an I cache.[/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]HTH,
    Iso[/size][/font][/color]
  • Arm Employee Badge
    Note: This was originally posted on 11th March 2013 at http://forums.arm.com

    That is a probably a question only the senior architects at ARM can answer with certainty.

    My suspicion is that it was simple to save space in the encoding.  At a given level the cache(s) will either be harvard (separate I & D) or unified.  Given that, it seems sensible to save some encoding space by doubling up some of the commands.