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data & unified cache

baskaran chidambaram
Note: This was originally posted on 9th March 2013 at http://forums.arm.com

In the A8 cache registers i see that the data cache tied to Unified cache - for enabling, cleaning etc. Any reason for this?

Regards
Baskaran
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  • Arm Employee Badge
    Note: This was originally posted on 11th March 2013 at http://forums.arm.com

    [color=#222222][font=arial, helvetica, sans-serif][size=2]> why there no separate configuration for Unified cache. why it has to be clubbed with Data cache? [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]At a given level in the cache hierarchy you will either have a separate I and D cache, or a unified cache. You never have both a D cache and a unified cache at the same level. [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]For 99% of ARM implementations you will have separate I and D at level 1, and a unified level 2. The usage of the set way logic selects which cache level you want to invalidate, so you can target either the D or the U cache depending on what level you have selected.[/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]You group the I cache by itself because it is fundamentally different to the other two - D and U can both contain modified data, the I cache cannot, so many encodings make no sense for an I cache.[/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]HTH,
    Iso[/size][/font][/color]
Reply
  • Arm Employee Badge
    Note: This was originally posted on 11th March 2013 at http://forums.arm.com

    [color=#222222][font=arial, helvetica, sans-serif][size=2]> why there no separate configuration for Unified cache. why it has to be clubbed with Data cache? [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]At a given level in the cache hierarchy you will either have a separate I and D cache, or a unified cache. You never have both a D cache and a unified cache at the same level. [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]For 99% of ARM implementations you will have separate I and D at level 1, and a unified level 2. The usage of the set way logic selects which cache level you want to invalidate, so you can target either the D or the U cache depending on what level you have selected.[/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]You group the I cache by itself because it is fundamentally different to the other two - D and U can both contain modified data, the I cache cannot, so many encodings make no sense for an I cache.[/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]
    [/size][/font][/color]
    [color=#222222][font=arial, helvetica, sans-serif][size=2]HTH,
    Iso[/size][/font][/color]
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