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data & unified cache

baskaran chidambaram
Note: This was originally posted on 9th March 2013 at http://forums.arm.com

In the A8 cache registers i see that the data cache tied to Unified cache - for enabling, cleaning etc. Any reason for this?

Regards
Baskaran
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  • Arm Employee Badge
    Note: This was originally posted on 11th March 2013 at http://forums.arm.com

    That is a probably a question only the senior architects at ARM can answer with certainty.

    My suspicion is that it was simple to save space in the encoding.  At a given level the cache(s) will either be harvard (separate I & D) or unified.  Given that, it seems sensible to save some encoding space by doubling up some of the commands.
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  • Arm Employee Badge
    Note: This was originally posted on 11th March 2013 at http://forums.arm.com

    That is a probably a question only the senior architects at ARM can answer with certainty.

    My suspicion is that it was simple to save space in the encoding.  At a given level the cache(s) will either be harvard (separate I & D) or unified.  Given that, it seems sensible to save some encoding space by doubling up some of the commands.
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